Loading…
Type: Software Design clear filter
arrow_back View All Dates
Monday, September 14
 

11:00 MDT

Queue Discipline: A Deep Dive into Lock-Free SPSC, MPSC, SPMC, and MPMC Queues in Modern C++
Monday September 14, 2026 11:00 - 12:00 MDT
Queues are the backbone of concurrent systems — yet most C++ developers treat them as a black box. Pick the wrong queue topology, misplace an alignas, or use the wrong memory order, and you pay for it in microseconds of latency, invisible cache thrashing, or subtle correctness bugs that only manifest under load. This talk is a rigorous, bottom-up treatment of the four canonical concurrent queue topologies: SPSC, MPSC, SPMC, and MPMC. We start with the hardware reality — how cache coherence protocols turn innocent struct layout into a performance disaster through false sharing — and build upward through the C++ memory model, atomic operations, and queue algorithm design. For each topology, we derive the minimal set of memory ordering guarantees required for correctness, show how to exploit producer/consumer asymmetry to eliminate unnecessary synchronization, and demonstrate how alignas(std::hardware destructive interference size) and deliberate padding can be the difference between 100ns and 10ns throughput. We dissect Dmitry Vyukov's MPMC ring buffer, the intrusive MPSC queue, and Michael-Scott's linked-list queue — not just their interfaces, but the why behind every memory order acquire and every phantom cache line. We then go beyond correctness into the practical engineering tradeoffs: bounded vs unbounded, throughput vs latency, contention vs coordination overhead. Real benchmark data shows how these decisions interact non-obviously — an MPMC queue can outperform MPSC under certain producer counts, and seq cst where you don't need it can quietly halve your throughput. Attendees will leave with a clear mental model for choosing and implementing the right queue for their threading topology, a checklist for false sharing audits, and battle-tested code patterns suitable for low-latency production systems.

Presenters
avatar for Anmol Singhal

Anmol Singhal

Gardening, My garden
Anmol has spent 5 years working as a quantitative developer at Goldman Sachs and IMC trading. Previously he completed his education from NYU and BITS Pilani. Most recently he developed multi threaded applications for trading application and improved software performance. He errs on... Read More →
Monday September 14, 2026 11:00 - 12:00 MDT
_5

14:00 MDT

Familiar C++ Patterns That Fail at Scale and the Design Shifts That Prevent Them
Monday September 14, 2026 14:00 - 15:00 MDT
Some of the most expensive C++ bugs are not caused by obscure language features. Instead, they emerge from code that looks reasonable: shared ownership that quietly extends lifetimes, singletons that become invisible dependencies, and performance-driven decisions that harden into architecture.

This talk examines these common design-level failure patterns in large-scale C++ systems. We cover three concrete design shifts:

Lifetimes: Shifting from shared ownership to explicit lifetime boundaries. Coupling: Shifting from implicit global coupling to injected dependencies. Interfaces: Replacing permissive APIs with constrained interfaces using std::span, std::optional, std::variant, and strong types.

Each shift is presented with the failure pattern it addresses, the solution, and the design rule it yields. Attendees will leave with practical heuristics for designing systems that are easier to reason about, test, and evolve: all grounded in real-world failures and the redesigns that fixed them.

Presenters
avatar for Divya Chandrasekar

Divya Chandrasekar

Software Engineering Team Lead, Bloomberg
Divya Chandrasekar is an Engineering Leader at Bloomberg, where she leads FXGO Orders, a trading platform within FXGO. She holds a master’s degree in Computer Engineering from the University of Florida and has held multiple engineering roles at Bloomberg. With a strong technical... Read More →
DD

Devpriya Dave

Devpriya Dave is a software engineer on the FX Options team at Bloomberg. While at Georgia Tech obtaining her master's degree, she helped design and build the system behind Georgia Tech's Machine Learning for Trading online course. She is passionate about STEM mentorship and is always... Read More →
Monday September 14, 2026 14:00 - 15:00 MDT
_2

15:15 MDT

Capability Routing Grid: From Decoupled Plugins to the Hardware Ceiling
Monday September 14, 2026 15:15 - 16:15 MDT
For C++ developers building modular applications or performance-critical loops, modern architecture often forces a painful compromise: you either build heavily decoupled systems that thrash the CPU cache, or you write rigid, tightly coupled code. Distributed builds mask the compile-time symptom — but the underlying coupling bleeds into the runtime hot path.

This talk presents the Capability Routing Grid (CRG), an architecture that refuses this compromise. CRG enables a zero-registry plugin system where modules self-register at link time, and polymorphic dispatch is reduced to an O(1) branchless array lookup — with no central registry, no Init() function, and no runtime search.

Three independent pillars, each usable standalone:

Pillar 1 — Linker-Driven Discovery: Build a fully decoupled plugin system without central registries or Init() boilerplate. Modules self-register via standard C++ static initialization — entirely automatic in monolithic builds, and requiring a single explicit sync-point call at DLL load time.

Pillar 2 — State and Behavior Separation: Enforce a strict architectural boundary between pure data structs and stateless capability objects. This separation — not a framework — is what keeps the hot path flat. Type erasure is available as an optional cold-path utility for cross-boundary routing, but is never required for performance.

Pillar 3 — O(1) Branchless Dispatch: Map multi-dimensional contextual states into a single flat lookup table using basic polynomial math. Because this layout never changes, the CPU branch predictor and hardware prefetcher maintain peak efficiency.

The final payoff: by collapsing capabilities into raw function pointers, the system hits the memory bandwidth ceiling — 33 GiB/s sustained throughput, with a per-dispatch tax of approximately 1.5 nanoseconds.

Data-Oriented Design is defined from scratch. A brief hardware cache primer precedes every performance claim. The entire architecture compiles on C++17 — no language extensions, no experimental flags, on any mainstream toolchain. The audience will leave thinking, "I could have written this" — because they can.

Attendees will learn how to: - Build self-registering plugins with zero shared headers, using standard static initialization across both monolithic and DLL builds - Apply state/behavior separation as an architectural discipline — keeping capabilities stateless and the hot path free of virtual overhead - Replace vtable dispatch with a flat array lookup across N behavioral dimensions — O(1) regardless of dimensionality - Cache resolved logic as raw function pointers and call them directly, reaching memory-bound throughput

Presenters
CT

Cyril TISSIER

Cyril Tissier is a Tech Lead at Ubisoft. Having joined the Montreuil studio in January 2014, he moved to the Annecy team in 2021. As a metaprogramming expert and the creator of an internal Advanced C++ training program, his primary goal has always been straightforward: to make the... Read More →
Monday September 14, 2026 15:15 - 16:15 MDT
_5

16:45 MDT

Using Type Erasure to Extend APIs You Don't Own: A Case Study From Audio Plugin Development
Monday September 14, 2026 16:45 - 17:45 MDT
Application developers sometimes hit a limitation of a 3rd-party library or framework. The Type Erasure design pattern can help us overcome such limitations without the need to change the 3rd-party API.

Type Erasure is a relatively complex design pattern that allows us to treat a set of unrelated classes as if they shared a common base class, while preserving value semantics. The downside is increased code bloat and code complexity as the pattern requires a significant amount of additional code.

There have been quite a few talks explaining HOW to implement Type Erasure, while the topic of WHEN has been rarely discussed. Should we always use type erasure instead of virtual polymorphism? And if not, then what are the criteria?

This talk will show a concrete example from the audio programming industry of how Type Erasure allowed adding new functionalities to the parameter class system of the JUCE C++ framework without changing its API. As such, the talk will be useful for application and library developers who use 3rd party libraries but need an extra degree of flexibility.

You will come out of the talk understanding

  • what Type Erasure is,
  • when to use it, and
  • how to implement it.
You don't need to understand Type Erasure, audio development, or JUCE to attend the talk; the necessary minimum will be explained during the talk.

Presenters
avatar for Jan Wilczek

Jan Wilczek

Audio Programming Consultant & Coach, WolfSound
I am an audio programming consultant and educator, the creator of TheWolfSound.com blog and YouTube channel dedicated to audio programming. I also host the WolfTalk podcast, where I interview developers and researchers from the audio industry.
I created "DSP Pro," an online course... Read More →
Monday September 14, 2026 16:45 - 17:45 MDT
_2
 
Share Modal

Share this link via

Or copy link

Filter sessions
Apply filters to sessions.
Filtered by Date -