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Thursday, September 17
 

09:00 MDT

Tying up Loose Threads: Making Your Project No-GIL Ready
Thursday September 17, 2026 09:00 - 09:30 MDT
Python's Global Interpreter Lock, which determines which single thread can execute native Python code and call C API functions, simplifies writing multithreaded code. By default, the most popular C++ bindings to this API, pybind11 and Cython, implicitly enables the GIL by default. However, sticking with this execution model leaves out extra performance afforded by modern multicore CPUs with hyperthreading, as automatic locking and unlocking of the GIL does not scale well with thread counts, especially in performance-sensitive workloads.

The newfangled free-threaded interpreter promises salvation when running either pure Python code or with compiled extensions. General multithreading rules apply (prefer thread-local variables, using locks to prevent simultaneous access of shared data), but when dealing with projects containing compiled extensions that directly or indirectly interface with Python's C API, more porting rules also apply.

Key porting tips, including projects using the Limited API, include: port native code away from C API functions that avoid borrowed references because they aren't thread-safe; modify unit tests to catch concurrency bugs arising from assuming the presence of the GIL; and extend CI coverage of Python interpreters both for testing and to build free-threaded compatible wheels.

Presenters
CL

Charlie Lin

Freelancer, N/A
Thursday September 17, 2026 09:00 - 09:30 MDT
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09:00 MDT

Back to Basics: Loops in C++
Thursday September 17, 2026 09:00 - 10:00 MDT
A fundamental control structure of each programming language are loops. And we all expect them to be simple and self explanatory. However, C++ would not be C++, if there would be no tricky details to learn and respect about loops in C++.

This talk takes its time to discuss the various ways and approaches to program loops in C++. Beside basic while and for loops, we talk about the range-based for loop, and all the extensions recently added to these control structures.

In addition, we will look at other ways to program loops in C++, such as using algorithms and how to deal with parallel computing in a loop.

As a result you get a deeper understanding of the various ways loops can be programmed in Modern C++ so that you know better how to use them in practice.

Presenters
Thursday September 17, 2026 09:00 - 10:00 MDT
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09:00 MDT

Writing Low-Latency C++: Predictability, Cache, and the Architectures Underneath
Thursday September 17, 2026 09:00 - 10:00 MDT
In low-latency C++, correctness is table stakes. What separates good systems from great ones is predictability — the ability to hit your deadline not just on average, but at the 99th and 99.9th percentile, where real workloads live. Latency is a feature, and if you don't design for it explicitly, you lose it accidentally.

This talk is a practitioner's guide to writing C++ that behaves predictably under load, drawn from experience building and tuning low-latency systems on Microsoft's Azure Core platform. We start from the mental models that matter most — CPU-centric thinking, the latency stack from L1 to DRAM, and why minimizing work, unpredictability, and memory movement is the foundation of everything else — and then work through the layers of the stack where latency is won or lost in practice.

Through live demos and benchmark data on both x86 and ARM, we'll cover:

STL containers as latency contracts — why most latency bugs start with the wrong container, the real cost of dynamic reallocation, and the measurable wins from reserve() and custom allocators.

Memory layout and cache behavior — struct layout and alignment (and how it differs on x86-64 vs. ARM64), AoS vs. SoA trade-offs, hot/cold data separation, false sharing, NUMA, and TLB pressure.

Atomics vs. mutexes — when atomics actually lose to mutexes, why architecture and memory model dictate the answer, and how to choose between them in real code.

Threading and scheduling — fixed vs. dynamic thread pools, context-switch and migration costs, and why understanding the OS is half the battle.

Benchmarking and observability — why microbenchmarks lie, how to avoid measurement bias and jitter, why latency histograms beat averages, and why "absolute benchmark" is a myth.

You'll leave with a practical playbook for designing and measuring low-latency C++ systems, an honest understanding of why benchmarks from one machine rarely generalize to another, and a sharper instinct for the silent killers — allocations, branches, cache misses, and synchronization primitives — that don't show up in code review but do show up in production.

Presenters
avatar for Sampad Acharya

Sampad Acharya

Senior Quant Developer, Fixed Income Trading, Bloomberg
Sampad Acharya is a senior software engineer at Bloomberg, where he specializes in low‑latency, cache‑optimized C++ systems for trading and real‑time environments. He has worked in software development for six years. Sampad is deeply interested in how algorithms behave in the... Read More →
Thursday September 17, 2026 09:00 - 10:00 MDT
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09:35 MDT

[[musttail]]-ling Our Way to a Faster Python Interpreter and New JIT Compiler
Thursday September 17, 2026 09:35 - 10:05 MDT
In CPython 3.14, we introduced an alternative interpreter implementation. This implementation used [[musttail]] , an experimental C/C++ feature that tells the compiler to enforce tail calls. Against the previous interpreter using computed gotos/switch-case, the new interpreter style shows 2%--15% performance improvement (i.e. geometric mean running time), and is more resilient against certain types of compiler bugs. This feature is already supported by Clang, GCC, and MSVC, and is also the center of a draft proposal targeting C++29. In this talk, I’ll cover the story of getting this feature into the Python interpreter, our collaboration with compiler developers, and the potential wider impact on the C++ community. I’ll also cover interesting use cases of this feature other than for writing interpreters, such as for automatically generating a simple Just in Time (JIT) compiler.

Presenters
KJ

Ken Jin Ooi

Ken Jin Ooi is a Python maintainer since 2021 and is also currently a contractor for OpenAI. His Python work revolves around the performance of the Python interpreter, which is written in a subset of C11 that is mostly compatible with C++.
Thursday September 17, 2026 09:35 - 10:05 MDT
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14:00 MDT

C++ in the Age of AI: How Visual Studio Is Evolving
Thursday September 17, 2026 14:00 - 15:00 MDT
For almost 30 years, Visual Studio has been a core part of the C++ developer's toolkit on Windows. This year, we're building on that foundation with investments across three themes: making the IDE faster and more responsive for large codebases, advancing compiler conformance and runtime performance, and integrating AI-powered workflows that help you debug, refactor, and optimize more effectively. Beyond the IDE, we'll show you how AI-powered command-line tools can become a natural part of your development process. This session combines demos and practical guidance so you can get the most out of these tools right away. Come with curiosity, leave with new techniques you can apply immediately.

Presenters
avatar for David Li

David Li

Game Developer Product Manager, Microsoft
David Li is the Game Developer Product Manager at Visual Studio with 12 years of experience in the software industry. As a gamer himself, David is especially passionate about enhancing game developer productivity through improving tooling for Visual Studio. In his free time, he enjoys... Read More →
avatar for Augustin Popa

Augustin Popa

Senior Product Manager, Microsoft
I am a product manager on the Microsoft C++ team, working on the Visual Studio IDE and vcpkg, the C/C++ package manager.
Thursday September 17, 2026 14:00 - 15:00 MDT
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14:00 MDT

Using Modules in a Real Project
Thursday September 17, 2026 14:00 - 15:00 MDT
C++20 modules are finally usable end to end, from your own modules to 'import std;' The functional build-system support with real diagnostics. This talk teaches modules the way #include was once taught: with small files, a build, and concrete use cases. Modules stopped being experimental somewhere around 2025. This session builds the mental model from scratch: what a primary module interface unit is, how partitions and implementation units fit together, and, crucially, how import differs from #include in ways that matter day to day. It uses a small library, exposes it as a module, splits it across partitions, consumes import std; and observes the compile-time effect. Then it answers the questions every team hits in week one: how modules interact with macros, with templates in headers, with header-only dependencies, and with a mixed codebase that can't convert everything at once. The examples will be using CMake, clang and recent gcc. You will leave able to structure a small library as a module, explain why a macro didn't cross a module boundary, and plan an incremental adoption that doesn't require converting the whole tree.

Presenters
avatar for Erez Strauss

Erez Strauss

Strat - Sr Software Engineer, Eisler Captal
Erez Strauss worked in Banks and Hedge Funds while focused on low latency systems.
Thursday September 17, 2026 14:00 - 15:00 MDT
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14:00 MDT

When Zero-Cost Abstractions Aren’t Zero-Cost
Thursday September 17, 2026 14:00 - 15:00 MDT
Zero-cost abstractions are a foundational idea in C++, promising expressive, high-level code without sacrificing performance. However, developers often encounter unexpected costs when using modern abstractions in practice, even when the code appears idiomatic and well-designed.

This talk explores the assumptions behind zero-cost abstractions and examines what happens when those assumptions no longer hold. Through concrete examples drawn from modern C++ — including ranges and views, type erasure, allocators, and other common abstractions — we will examine how factors such as optimizer visibility, inlining boundaries, allocation behavior, and runtime flexibility influence performance.

This talk treats abstraction as a powerful engineering tool, examining the limits of its zero-cost guarantees in real-world systems. We will look at how seemingly small design choices can introduce hidden costs, why those costs are often difficult to spot through inspection alone, and how to recover performance without abandoning good design or readability.

Attendees will leave with a clearer understanding of when abstractions are truly zero-cost, how to recognize situations where they are not, and how to make informed tradeoffs between expressiveness, flexibility, and performance in modern C++.

Presenters
avatar for Steve Sorkin

Steve Sorkin

Senior Software Engineer, Bloomberg
Steve Sorkin has been at Bloomberg since 2019, where he is a senior software engineer. He is enthusiastic about writing clean, scalable, and maintainable code for use in low latency and high throughput applications. Prior to joining Bloomberg, Steve worked as a securities/derivatives... Read More →
Thursday September 17, 2026 14:00 - 15:00 MDT
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15:15 MDT

Leveraging LLM to Generate Unittests for Notifiers in Taskflow
Thursday September 17, 2026 15:15 - 16:15 MDT
Notifiers are a critical synchronization primitive in task-parallel programming systems such as Intel TBB and Taskflow, responsible for efficiently sleeping and waking worker threads as tasks become unavailable and available over and over again, directly impacting scheduler throughput and latency. Correctness here is non-negotiable: a single missed wakeup can significantly hamper the performance of an entire program. Yet writing strong unit tests for notifiers is notoriously difficult, because the bugs they target, lost wakeups, spurious wakes, race conditions, are timing-dependent, non-deterministic, and often only surface under specific thread interleavings that are hard to force reliably.

The problem is compounded in practice. Notifier implementations evolve constantly: small algorithmic tweaks, memory ordering changes, and refactors across systems demand a fresh round of carefully constructed tests. This is tedious, expertise-heavy work that takes a lot of time and engineering effort. In this talk, we explore using Large Language Models (LLMs) to automate the generation of the unit tests for notifiers. Specifically, we will demonstrate how LLM-generated tests, guided by proper prompts can systematically stress the two-phase wait protocol across Notifiers in Taskflow. We will show this in a widely used Notifier implemented in Taskflow. We are able to find an undiscovered bug that has been existing in the project.

Presenters
SS

Snikitha Siddavatam

Snikitha Siddavatam is a Computer Science and Data Science student at the University of Wisconsin-Madison, expected to graduate in May 2027, with coursework spanning machine learning, artificial intelligence, distributed systems, data visualization, and advanced algorithms. Snikitha... Read More →
Thursday September 17, 2026 15:15 - 16:15 MDT
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15:15 MDT

The Latency Slippage: Understanding the Hidden Costs of Caching for Low Latency C++
Thursday September 17, 2026 15:15 - 16:15 MDT
Choosing cache-friendly data structures is a well-known optimization, but it's rarely the whole story. This talk goes deeper, exploring the hardware mechanics that dictate real-world performance and showing where significant gains are still left on the table.

We'll start from the ground up: what actually happens inside the cache hierarchy when your code issues a memory read or a software prefetch? Understanding the hardware lets us answer, when you should prefetch manually, and when you should trust the hardware prefetcher.

From there, we'll examine the invisible cost of multi-core C++. Cache coherency protocols (MESI/MOESI) can silently degrade performance through false sharing, RFO stalls, and coherency storms. We'll walk through how to diagnose these issues using hardware performance counters and how to eliminate them.

Additionally, we will contrast these behaviors across the data cache (DCache) and instruction cache (ICache), and analyze how Translation Lookaside Buffers (TLBs) impact overall memory read latency.

Finally, we'll tie it all together by combining hardware insight with application profiling data to arrive at practical strategies for low latency C++, packaged as an application-aware memory allocator.

Presenters
SG

Sanchit Gupta

Sanchit Gupta graduated from Indian Institute of Technology, Madras with Honours in Bachelors of Technology in Computer Science and Engineering. Since graduating, Sanchit has worked for Graviton as a Low latency Software Developer
Thursday September 17, 2026 15:15 - 16:15 MDT
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16:45 MDT

Extending Google Test for Statistical Benchmarking, CUDA Profiling, and CI Performance Regression
Thursday September 17, 2026 16:45 - 17:15 MDT
Benchmarks shouldn't live in a different world from tests. Most C++ projects already use Google Test, but the moment performance enters the picture, developers reach for separate tools, separate workflows, and ad-hoc timing loops that don't survive contact with CI. This talk argues for a different default: treat performance measurements as first-class tests. They are written in the same harness, run in the same suite, and fail the same builds.

Using a real C++23 framework built on top of Google Test, the session shows what that looks like in practice. Semantic macros distinguish throughput, latency, and contention tests; built-in statistical analysis tracks medians, percentiles, and coefficient of variation. Adaptive thresholds scale with payload size, so tiny operations and multi-megabyte workloads aren't held to the same stability expectations.

Once benchmarking lives inside the test framework, the rest of the performance toolchain follows. Five CPU profiler backends drop in behind a single --profile flag: perf, gperftools, bpftrace, RAPL, and callgrind. Attaching a memory profile to a test prints bandwidth, efficiency, and a CPU-bound or memory-bound classification with no extra code. The same harness extends to CUDA through a fluent kernel builder that captures launch configuration, achieved occupancy, transfer overhead, multi-GPU scaling efficiency, and thermal throttling. Nsight Compute drops in through the same --profile flag.

The payoff is CI integration that's nearly automatic. A companion CLI tool compares baseline and candidate runs, applies statistical thresholds, posts markdown reports on pull requests, and fails the build on regressions. The result is a single workflow for performance verification that scales from a developer's laptop to a CI runner to a Jetson on a workbench, across hardware ranging from x86 to ARM to RISC-V.

Presenters
Thursday September 17, 2026 16:45 - 17:15 MDT
_4

16:45 MDT

Are You Smarter Than A Branch Predictor?
Thursday September 17, 2026 16:45 - 17:45 MDT
Are you smarter than a branch predictor? In this interactive, game-show themed session, the audience becomes the branch predictor: participants vote on which of two C++ snippets will run faster before we examine what actually happens on real hardware. The snippets are drawn from real world production code, and correct answers are rewarded with stress balls. Through these examples, we build a practical mental model of how modern CPUs handle control flow, and why even small branching decisions can have a significant impact on performance. A single mispredicted branch can stall a CPU pipeline for dozens of cycles, making control flow a hidden bottleneck in performance-critical systems. Using annotated assembly, performance counter data, and cross-platform comparisons, this talk explores branch prediction, misprediction costs, indirect calls and virtual dispatch, and the trade-offs between branches and conditional moves. We examine how compilers (GCC, Clang, MSVC) transform code under different optimization levels (such as -O2 and -O3), and highlight non-obvious cases where “branchless” code performs worse or behaves differently across architectures. The examples are intentionally small micro-benchmarks, but each exposes patterns that appear in real-world systems when control flow becomes the bottleneck. The session also covers how to design trustworthy micro-benchmarks and validate performance changes using hardware counters. Attendees will leave with a clearer understanding of how branches behave on modern processors, when to rely on compiler optimizations, and when to measure and optimize manually.

Presenters
avatar for Michelle D'Souza

Michelle D'Souza

Software Engineer, Bloomberg
Michelle Fae D’Souza is a Software Engineer at Bloomberg, where she develops C++ code for the company’s order-trade entry and modification (OTE API) solution, which streamlines trading activity for many firms in the financial world. She is an active member of Bloomberg's C++ Guild... Read More →
Thursday September 17, 2026 16:45 - 17:45 MDT
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16:45 MDT

Quicker Than Quick: Using Radix Sort to Make `std::stable_sort` Beat `std::sort`
Thursday September 17, 2026 16:45 - 17:45 MDT
This talk takes you through the research and optimization of radix sort, culminating in its integration into libc++.

You will learn : common pitfalls of radix sort implementations (non-binary digits, dynamic memory allocation, fragile interfaces), how to design a strict and high-performance interface (fixed digit size, external buffer, projection to integers), and how to overcome radix sort's main drawback — its lack of naturalness — with two counter-based optimizations and a hybrid merge scheme.

The result : on arrays of 60 int32 elements (18 for int8), radix sort starts beating std::sort ; on large arrays, it's up to 10x faster. Floating-point types (float/double/float16_t) are also supported via IEEE 754 bit transformations (sign and exponent inversion for negative numbers).

The key takeaway : in modern libc++, for integers and floats, std::stable_sort on random data is noticeably faster than std::sort . Life has become better, but also more complicated — choose your sorting algorithm wisely.

Presenters
DI

Dmitriy Izvolov

C++ Developer
Dmitry Izvolov graduated from MIEM (Moscow Institute of Electronics and Mathematics) with a degree in Applied Mathematics. Since then, he has worked as a programmer across diverse domains: DLP systems, information retrieval, cybersecurity, image processing, and speech synthesis. Currently... Read More →
Thursday September 17, 2026 16:45 - 17:45 MDT
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