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Subject: Performance clear filter
Monday, September 14
 

11:00 MDT

From 20 Nanoseconds to One: Optimizing Bishop, Rook, and Queen Move Generation in a Chess Engine
Monday September 14, 2026 11:00 - 12:00 MDT
A chess engine must search millions of positions per second. Move generation is often a bottleneck. Generating moves for knights, kings, and pawns are computationally cheap (~1 nanosecond). However, rooks, bishops, and queens (aka "sliding pieces") present a unique challenge: their movement depends on the placement of other pieces. This makes on-demand generation too slow (20+ nanoseconds) and naively-implemented lookup tables impractical (requiring zettabytes of RAM).

We will start by reviewing the core data structures in a chess engine and the logic behind move generation. Then, we will explore "magic bitboards", a perfect hashing technique that enables sliding piece move generation in ~1 nanosecond. We will look at how to implement this in modern C++, comparing hardware-specific instructions like PEXT (Parallel Bits Extract) against a portable software approach. Finally, we will discuss the practical challenges of generating the data structures required for magic bitboards, including the limitations of consteval and how to integrate build-time table generation into the build process using Bazel.

To ground these concepts, we will be referencing implementation details and code from my C++ chess engine, FollyChess.

Presenters
AN

Aryan Naraghi

Aryan Naraghi is a Staff Software Engineer at Google specializing in distributed systems. Over the past 14 years, he has built critical infrastructure across Google (including BigQuery, Cloud Run, Compute Engine, and Vertex AI) and previously led data strategy as Head of Data Analytics... Read More →
Monday September 14, 2026 11:00 - 12:00 MDT
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11:00 MDT

From Firmware to Screen: Real-Time Control, Simulation, and Visualization in C++23 With CUDA and Unreal Engine
Monday September 14, 2026 11:00 - 12:00 MDT
What does it take to build a real-time embedded control system in modern C++, simulate its environment, command it from a browser, and watch it fly in 3D — all from the same open source ecosystem? This talk follows that pipeline end-to-end: from a C++23 real-time framework that schedules deterministic control loops across POSIX hosts and bare-metal microcontrollers, to GPU-accelerated simulation with CUDA, to web-based operations and telemetry, to live 3D visualization in Unreal Engine.

Attendees will see how a unified runtime architecture can span embedded control, simulation, diagnostics, operations, and visualization without fragmenting into separate software stacks. The talk explores deterministic scheduling, zero-allocation real-time design, cross-platform deployment, and integrating CUDA compute kernels directly into scheduled control loops without blocking execution. It also covers tooling for validating deterministic real-time behavior, along with techniques for streaming telemetry and sensor data between simulation and visualization layers in real time.

The presentation includes live demonstrations of a quadcopter simulation flying a programmed trajectory with lidar feedback, and a full-fidelity aircraft simulation with closed-loop autopilot, engine dynamics, and atmospheric turbulence — both running through the same real-time framework and rendered live in Unreal Engine. Whether you build flight software, robotics systems, industrial controllers, or simulation infrastructure, this talk presents practical architectural patterns for modern real-time systems in C++ that bridge embedded devices, GPU compute, and interactive visualization.

Presenters
Monday September 14, 2026 11:00 - 12:00 MDT
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11:00 MDT

Same Bits Without Losing MIPS: Reproducible Numerics at Full Hardware Speed
Monday September 14, 2026 11:00 - 12:00 MDT
Floating point has a reputation for betrayal. Change the thread count, vector width, compiler flags, reduction tree, or target architecture, and the low bits can move. Parallel algorithms make this worse: the standard often specifies the operation, but not the numerical expression whose result must be reproduced. This talk asks a provocative question: what if reproducible numerics did not have to be slow?

We will show reproducible, deterministic implementations of reduce and scan that exhibit better error behavior on hostile floating-point workloads and can match or beat conventional standard-library implementations on realistic workloads. The trick is not to freeze the execution schedule. It is to specify the expression being computed, then let the implementation use SIMD, threading, blocking, tiling, and platform-specific strategies to compute that expression efficiently.

The key idea, developed through C++ standardization work such as P4016R0 and P4229R0, is reproducibility by reproducing the computation. Instead of asking the implementation to promise a particular schedule, we give the calculation a named expression. Once that expression is chosen, changing the thread count, vector width, chunking, or blocking strategy does not silently change the answer.

A reproducible scan makes this harder than reduce because it does not expose only one final value. It exposes every prefix. A reproducible final sum is not enough if the intermediate results still drift. We will show how expression and observation contracts make those prefixes reproducible without forcing the computation back into a slow sequential order.

Then we go below the algorithm layer, to the places where bits usually escape: FMA contraction, denormals, floating-point environment choices, math-library approximations, and vectorized transcendental functions. The goal is not to get the same answer by turning off the hardware. We will show reproducible vectorized primitives, including transcendental functions, running at speeds comparable to established vector math libraries while preserving a cross-platform numerical contract.

Finally, we put the whole stack under stress: a heterogeneous numerical pipeline across x86-64, Apple Silicon, and CUDA. The data is deliberately hostile, with high cancellation rates and fragile intermediate states. The aim is not to pass friendly benchmark cases, but to reproduce the specified computation, including the same intermediate failures, not just the same final answer, bit for bit, across CPUs, GPUs, and toolchains.

Presenters
avatar for Andrew Drakeford

Andrew Drakeford

Director, UBS
Andrew Drakeford A Physics PhD who started developing C++ applications in the early 90s at British Telecom labs. For the last two decades, he has worked in finance developing efficient calculation libraries and trading systems in C++. His current focus is on making quant libraries... Read More →
Monday September 14, 2026 11:00 - 12:00 MDT
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11:00 MDT

Queue Discipline: A Deep Dive into Lock-Free SPSC, MPSC, SPMC, and MPMC Queues in Modern C++
Monday September 14, 2026 11:00 - 12:00 MDT
Queues are the backbone of concurrent systems — yet most C++ developers treat them as a black box. Pick the wrong queue topology, misplace an alignas, or use the wrong memory order, and you pay for it in microseconds of latency, invisible cache thrashing, or subtle correctness bugs that only manifest under load. This talk is a rigorous, bottom-up treatment of the four canonical concurrent queue topologies: SPSC, MPSC, SPMC, and MPMC. We start with the hardware reality — how cache coherence protocols turn innocent struct layout into a performance disaster through false sharing — and build upward through the C++ memory model, atomic operations, and queue algorithm design. For each topology, we derive the minimal set of memory ordering guarantees required for correctness, show how to exploit producer/consumer asymmetry to eliminate unnecessary synchronization, and demonstrate how alignas(std::hardware destructive interference size) and deliberate padding can be the difference between 100ns and 10ns throughput. We dissect Dmitry Vyukov's MPMC ring buffer, the intrusive MPSC queue, and Michael-Scott's linked-list queue — not just their interfaces, but the why behind every memory order acquire and every phantom cache line. We then go beyond correctness into the practical engineering tradeoffs: bounded vs unbounded, throughput vs latency, contention vs coordination overhead. Real benchmark data shows how these decisions interact non-obviously — an MPMC queue can outperform MPSC under certain producer counts, and seq cst where you don't need it can quietly halve your throughput. Attendees will leave with a clear mental model for choosing and implementing the right queue for their threading topology, a checklist for false sharing audits, and battle-tested code patterns suitable for low-latency production systems.

Presenters
avatar for Anmol Singhal

Anmol Singhal

Gardening, My garden
Anmol has spent 5 years working as a quantitative developer at Goldman Sachs and IMC trading. Previously he completed his education from NYU and BITS Pilani. Most recently he developed multi threaded applications for trading application and improved software performance. He errs on... Read More →
Monday September 14, 2026 11:00 - 12:00 MDT
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14:00 MDT

Thinking Low Level, Writing High Level
Monday September 14, 2026 14:00 - 15:00 MDT
An overview of contemporary hardware platforms and how software engineering and design practices and methodologies could help in building performant systems, with a particular focus on low level optimizations. Contrary to attempting direct low level software engineering for addressing performance specifics, this talk would focus on how higher level abstractions could and should be used, and how a software engineer could help the compiler to “do the right thing”. The trend of moving software engineering focus upward to constructs that have a tendency of hiding the specific of the underlying platform is quite clear – and there certainly are very good reasons for such a paradigm change.

Performance matters. Premature optimization is evil. Is there anything in between those two extremes? How feasible is it to rely on the abstraction of the platform as hidden by the compiler and the corresponding libraries and language constructs, expecting that it will be able to realize the intended lower level optimizations? How much of hints and specifics would one need to expose for the compiler to be able to get the equivalent of direct low level approach? What is the right balance between expressing application logic via higher level construct yet still being able to gain the performance benefits compared relying on the low level specifics?

Looking from the practical applicability of lambdas, iterators, ranges, coroutines, error handling, and safe(r) memory access, the talk would attempt to cover a set of use cases with a focus on analysis of what could be done for focusing on performance.

The overall goal of the talk is not to go deep into low level aspects; the goal is to explain that one needs to be aware of such low level details while operating on the higher level constructs.

Presenters
IB

Ignas Bagdonas

Principal Architect, Equinix
Ignas Bagdonas has been involved in network engineering field for over two decades, covering operations, deployment, design, architecture, development, and standardization aspects. He has worked on multiple large SP and enterprise networks worldwide, participated in many of the world's... Read More →
Monday September 14, 2026 14:00 - 15:00 MDT
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15:15 MDT

The journey to "/W4 /WX": How hard could it be?
Monday September 14, 2026 15:15 - 16:15 MDT
Building on the recent work of improving the quality of Sea of Thieves' codebase by upgrading from C++14 to C++20, this talk will focus on the work that has went into enabling warnings as errors on the game, and more.

Rare will discuss the motivations behind wanting to crank up the warning level, and to flick the "warnings as errors" switch after 10 years of development in their multi-million line Unreal Engine code base.

What were the challenges? How much effort did it take? Was it worth it? Did we find any bugs? Did we stop at just "/W4 /WX"? What warnings did we find the most useful? What warnings were deemed unhelpful? All of these questions and probably more will be answered throughout this session.

Presenters
avatar for Keith Stockdale

Keith Stockdale

Senior Software Engineer, Rare Ltd
Keith Stockdale is a Northern Irish senior software engineer who has been working on the Engine and Rendering teams at Rare Ltd for the last 8 years working on Sea of Thieves. At Rare, Keith's main areas of focus are involved in maintaining and creating general purpose simulations... Read More →
Monday September 14, 2026 15:15 - 16:15 MDT
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15:15 MDT

std::simd Without Compromise: Making SIMD in C++26 and Beyond as Fast as Silicon Allows
Monday September 14, 2026 15:15 - 16:15 MDT
For thirty years, SIMD has been the preserve of experts. Writing the fastest C++ has meant hand-written intrinsics, locking code to one architecture, and parallel implementations maintained across every instruction set you ship to. Auto-vectorization can help, but optimizers may give up in complex scenarios where iteration independence isn't obvious. C++26 changes that by putting SIMD in the hands of every C++ programmer, bringing portable, expressive data parallelism into the standard library.

For the engineers who have spent decades writing intrinsics in telecoms, finance, HPC, and embedded systems, migration to std::simd is only worthwhile if it preserves the performance they have fought to achieve. Every cycle counts when code runs tens of thousands of times per second, for years on end, and a portable abstraction that costs ten percent is not a win. The bar for adoption is therefore high: the abstraction must be measurably cheap, the generated code must match hand-written intrinsics, and the tricks and techniques those engineers rely on must all be expressible in the library, not lost in translation.

This talk takes the practitioner's view, aimed squarely at the engineers who write real intrinsics code today and need to know whether std::simd can replace it. It starts with what modern SIMD hardware actually offers, grounding std::simd in real silicon. It then works through the main features of C++26's std::simd with worked examples drawn from the patterns that recur in production intrinsics code, accessible to programmers new to the library and detailed enough for intrinsics veterans to map against their own kernels with all their accumulated tricks and techniques. A look under the hood at our implementation shows how careful API design and aggressive use of hardware features make the abstraction as cheap as the target architecture allows, and how the library fills the gaps on weaker targets with implementations that an expert library author can write once on behalf of every user. The talk closes with a preview of the C++29 proposals being written now to close the remaining gaps, so that std::simd becomes a clear win even for the most performance-critical code.

Presenters
avatar for Ruslan Arutyunyan

Ruslan Arutyunyan

Ruslan is a Senior Middleware Development Engineer specializing in parallel and threading runtimes. He joined Intel in 2017 and has experience in the autonomous driving domain, where he led the development of two libraries. Currently, Ruslan is the lead developer of oneAPI DPC++ library... Read More →
avatar for Daniel Towner

Daniel Towner

Principal Software Engineer, Intel
Dr Daniel Towner is a Principal Systems Engineer at Intel, where he has spent the last two decades helping telecoms software extract every last cycle from modern hardware. With 25 years in the industry behind him, including 12 years as a GCC port maintainer, he now splits his time... Read More →
Monday September 14, 2026 15:15 - 16:15 MDT
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15:15 MDT

Capability Routing Grid: From Decoupled Plugins to the Hardware Ceiling
Monday September 14, 2026 15:15 - 16:15 MDT
For C++ developers building modular applications or performance-critical loops, modern architecture often forces a painful compromise: you either build heavily decoupled systems that thrash the CPU cache, or you write rigid, tightly coupled code. Distributed builds mask the compile-time symptom — but the underlying coupling bleeds into the runtime hot path.

This talk presents the Capability Routing Grid (CRG), an architecture that refuses this compromise. CRG enables a zero-registry plugin system where modules self-register at link time, and polymorphic dispatch is reduced to an O(1) branchless array lookup — with no central registry, no Init() function, and no runtime search.

Three independent pillars, each usable standalone:

Pillar 1 — Linker-Driven Discovery: Build a fully decoupled plugin system without central registries or Init() boilerplate. Modules self-register via standard C++ static initialization — entirely automatic in monolithic builds, and requiring a single explicit sync-point call at DLL load time.

Pillar 2 — State and Behavior Separation: Enforce a strict architectural boundary between pure data structs and stateless capability objects. This separation — not a framework — is what keeps the hot path flat. Type erasure is available as an optional cold-path utility for cross-boundary routing, but is never required for performance.

Pillar 3 — O(1) Branchless Dispatch: Map multi-dimensional contextual states into a single flat lookup table using basic polynomial math. Because this layout never changes, the CPU branch predictor and hardware prefetcher maintain peak efficiency.

The final payoff: by collapsing capabilities into raw function pointers, the system hits the memory bandwidth ceiling — 33 GiB/s sustained throughput, with a per-dispatch tax of approximately 1.5 nanoseconds.

Data-Oriented Design is defined from scratch. A brief hardware cache primer precedes every performance claim. The entire architecture compiles on C++17 — no language extensions, no experimental flags, on any mainstream toolchain. The audience will leave thinking, "I could have written this" — because they can.

Attendees will learn how to: - Build self-registering plugins with zero shared headers, using standard static initialization across both monolithic and DLL builds - Apply state/behavior separation as an architectural discipline — keeping capabilities stateless and the hot path free of virtual overhead - Replace vtable dispatch with a flat array lookup across N behavioral dimensions — O(1) regardless of dimensionality - Cache resolved logic as raw function pointers and call them directly, reaching memory-bound throughput

Presenters
CT

Cyril TISSIER

Cyril Tissier is a Tech Lead at Ubisoft. Having joined the Montreuil studio in January 2014, he moved to the Annecy team in 2021. As a metaprogramming expert and the creator of an internal Advanced C++ training program, his primary goal has always been straightforward: to make the... Read More →
Monday September 14, 2026 15:15 - 16:15 MDT
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16:45 MDT

AEMBER: Modern Embedded C++ Without the Chaos
Monday September 14, 2026 16:45 - 17:45 MDT
Building embedded systems wastes time on infrastructure instead of features. Before running application logic, developers lose hours bootstrapping init systems, wiring services, debugging startup failures, and fighting tooling never designed for constrained or early-boot environments. AEMBER is a developer-first PID1 (init system) that eliminates this overhead by providing a modern C++ runtime for process supervision, container orchestration, and service management - letting you focus on your application, not your plumbing.

This talk demonstrates how C++23 enables robust embedded systems without sacrificing performance. We'll explore std::expected for exception-free error handling, if consteval for compile-time optimization paths, and deducing this for zero-overhead policy classes. You'll see how monadic operations compose system calls into clean pipelines, and how modern C++ features build type-safe APIs for namespaces, cgroups, and process management.

Starting from main(), we'll trace AEMBER's architecture: how components compose, how errors propagate through std::expected chains, and how C++23 patterns enable embedded systems to be both safe and fast. We'll wrap up with a live demo showing AEMBER managing containers and services in real-time. You'll leave with concrete techniques for building maintainable embedded infrastructure using cutting-edge C++.

Presenters
avatar for Arian Ajdari

Arian Ajdari

Software Engineer, Bertrandt GmbH
Arian Ajdari is a Software Engineer working on cutting-edge applications in the field of smart home appliances. His daily work includes discussions with clients, gathering requirements, building use-cases and implementing different solutions using C++. Arian possesses a deep understanding... Read More →
Monday September 14, 2026 16:45 - 17:45 MDT
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Tuesday, September 15
 

09:00 MDT

Implementing Flat Containers: Design and Optimisations in libc++'s flat_{set, map}
Tuesday September 15, 2026 09:00 - 10:00 MDT
This talk presents some design choices, compromises, and optimisations of the implementations of std::flat map and std::flat set. It will cover a brief design history of the original paper regarding the class layout, libc++'s best effort to provide strong exception guarantee on those containers, compromise on the iterator choices between SCARY and more strongly typed, some optimisations on various operations and some tips about avoiding running some issues with these containers.

Presenters
avatar for Hui Xie

Hui Xie

Senior Software Developer, QRT
Hui Xie is a C++ software developer at Qube Research and Technologies in the finance industry. He is a member of the standard committee WG21 and the UK national body BSI. He usually contributes to the ranges study group SG9. He is also an active contributor to libc++, the clang's... Read More →
Tuesday September 15, 2026 09:00 - 10:00 MDT
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09:00 MDT

Processor Design and C++ Memory Models
Tuesday September 15, 2026 09:00 - 10:00 MDT
std::atomic and std::memory_order are utterly opaque abstractions. It feels like they were put in place to hide some monstrosity that is too complex for mortals to comprehend, and inevitably when trying to understand the underlying reality, the explanations end with 'the processor does weird things' and 'think about it as if...'.

Well, 'think about it as if' no more. In this talk we'll present the gory and wonderful mechanics of cache coherence protocols, store buffers, cache invalidation queues and the in-processor load-store-queue. We'll explain how modern hardware design makes different cores have different views of memory, and what fences and read-modify-write instructions do exactly - for both x86/64 and ARM/RISC-V (which are sometimes dramatically different).

This is an advanced low-level talk located at the borderline of software development and electrical engineering, discussing topics rarely - if ever - discussed at C++ conference talks.

Presenters
avatar for Ofek Shilon

Ofek Shilon

Senior Developer, Speedata
A Mathematics MA by training, but a 20Y C++ developer, writer and speaker in both the Linux and MS universes. Member of the maintainers team of Compiler-Explorer (==godbolt). Fascinated by compilers, debuggers and pretty much anything low level. Fiercely hated by his cat for no apparent... Read More →
Tuesday September 15, 2026 09:00 - 10:00 MDT
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09:00 MDT

Death by a Thousand Tape Entries: Low-Overhead Automatic Differentiation for Scientific and Financial C++
Tuesday September 15, 2026 09:00 - 10:00 MDT
Reverse-mode automatic differentiation (AD) computes exact gradients with respect to thousands of inputs in roughly the time of a single function evaluation. If you write numerical C++ for finance, scientific computing, or ML and you care about performance, this talk will show you where AD overhead actually comes from and what to do about it.

A straightforward operator-overloading implementation records every arithmetic operation onto a tape and replays it backward to propagate derivatives. On real numerical code this easily introduces 50-100x overhead, and most of that has nothing to do with calculus. It is heap allocation on every operation. It is cache misses walking the tape backward. It is branch mispredictions at memory chunk boundaries. It is recording tape entries for operations where none of the operands are even being differentiated.

We work through a series of C++ techniques that bring this down to around 4x on production code in finance. The two that matter most: a chunked arena allocator with cache-line alignment and branch-prediction hints that turns the recording hot path into a pointer bump and a store, and expression templates that collapse an entire right-hand side into one tape push with all derivatives accumulated in a compile-time-sized stack buffer. We pull up compiler output to show the abstraction really does compile away.

After the big two, we get into the smaller wins that are still worth knowing about: skipping zero adjoints during the backward sweep to exploit sparsity, picking derivative formulas at compile time that reuse the forward result instead of recomputing it, and demoting active-times-passive operations from binary to unary to halve their tape footprint. We also show how a should-record check propagated through the expression tree lets the tape skip entire statements when no operand is active, and how aggressive inlining lets the compiler eliminate these checks entirely for passive subexpressions, so the cost of asking is zero when the answer is no. We benchmark each one in isolation on four numerical workloads ranging from 8 to 161 sensitivities, so you can see what each technique is actually worth.

Presenters
Tuesday September 15, 2026 09:00 - 10:00 MDT
_5

14:00 MDT

What Are We Synchronizing?
Tuesday September 15, 2026 14:00 - 15:00 MDT
Atomic memory ordering is often taught operationally: Use acquire here, release there, and perhaps add a fence “to be safe.” This approach tends to produce cargo-cult synchronization, where atomic operations are selected mechanically without a clear understanding of what information is actually being propagated between threads. In practice, memory ordering is not about memorizing enum values, but about establishing which facts become visible to which observers, and when.

This talk approaches atomic synchronization from first principles. Beginning with the fundamental ideas of publication, visibility, ownership transfer, and synchronization edges, the talk incrementally develops several concurrent structures drawn from real asynchronous systems. Case studies include outstanding-work reference counting, a multi-producer singly-linked publication structure, a concurrently-mutated doubly-linked intrusive list, and the coordination machinery underlying a concurrent operation with multiple concurrent completion modalities. Each structure is used to derive the synchronization requirements imposed by its invariants, rather than selecting memory orderings mechanically.

Along the way, the talk explores the practical meaning of relaxed operations, acquire/release synchronization, and atomic thread fences. Particular attention is paid to understanding what each actually does, when it is necessary, and when it has become a decorative synchronization cargo cult. The goal is not simply to present lock-free algorithms, but to develop a principled way of reasoning about memory visibility and synchronization in real concurrent systems.

Presenters
avatar for Robert Leahy

Robert Leahy

Robert Leahy is a C++ systems engineer specializing in the design of C++ libraries and high-performance infrastructure. Over the past decade he has built latency-sensitive financial systems, contributed to patented database technology, and developed production software for processing... Read More →
Tuesday September 15, 2026 14:00 - 15:00 MDT
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14:00 MDT

Inside a Small Game Engine: An Architecture Tour in Modern C++
Tuesday September 15, 2026 14:00 - 15:00 MDT
According to VGInsights, about 10% of games released on Steam in 2024 used a custom engine, but those games represent 41% of units sold. Most "how an engine works" talks come from the AAA end of that distribution. This one comes from the other end of that distribution: a teaching-scale engine, where every system has to be small enough to understand from first principles. The problems are the same as in a big engine, but the smaller surface is what makes the architecture legible.

In this talk, we'll walk the spine of the engine in modern C++: allocators and handles in the core, the job system, the graphics abstraction question, the asset pipeline split between pipeline-time and runtime, and scene representation including ECS. We finish on serialization, where C++26 reflection (P2996) offers a path past today's reliance on macros and external code generators.

Presenters
avatar for Elias Farhan

Elias Farhan

Head of Department, SAE Institute Geneva
Elias Farhan is the head of the Games Programming department at SAE Institute Genève, as well as founder of the RGB Games Programming Conference.
Tuesday September 15, 2026 14:00 - 15:00 MDT
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14:00 MDT

Breaking the Speed Limit: Building a High-Throughput Hashing Engine With C++26
Tuesday September 15, 2026 14:00 - 15:00 MDT
Modern storage hardware has evolved at a breakneck pace. PCIe Gen 5 NVMe drives can push data at 10 GB/s, yet standard C++ file abstractions often leave them starving for data. Many developers think they need to abandon portability in favor of unmaintainable, OS-specific kernel bypasses to achieve the throughput necessary to saturate these drives. This session is for developers writing high-throughput, performance-critical applications who want to hit bare-metal speeds without sacrificing clean architecture, cross-platform support, or type safety.

Using a high-throughput cryptographic hashing engine as a concrete case study, this presentation demonstrates how to design a hardware-saturating data pipeline built entirely on the idioms of C++26. We will explore how the mathematical design of an algorithm - specifically BLAKE3's binary Merkle tree structure - can be mapped directly to wide SIMD vector lanes and concurrent CPU cores. We will walk through an execution model that completely bypasses the OS page cache, orchestrates memory without heap allocations on the hot path, and unifies OS kernel quirks in a portable way.

By the end of this presentation, you will learn how to replace rigid thread pools with lock-free, asynchronous execution graphs using Sender/Receiver paradigms (std::execution) and vectorization (std::simd). Crucially, we will focus on the build engineering required to make this work today. We will cover how to use advanced CMake tooling to safely compile multi-architecture vector binaries from a single source of truth, how to prevent LTO cross-contamination, and how to structure your pipeline today to seamlessly absorb upcoming C++ features in a world of trailing vendor toolchains.

Presenters
YS

Yannic Staudt

co-founder, tipi.build
Tuesday September 15, 2026 14:00 - 15:00 MDT
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15:15 MDT

Lock-Free Timer Scheduling With C++ Atomics
Tuesday September 15, 2026 15:15 - 16:15 MDT
Applications that present rapidly changing market data to human users face a practical challenge: updates may arrive thousands of times per second, but humans only benefit from periodic refreshes. Efficiently coalescing and scheduling that work without overwhelming CPU resources becomes a concurrency problem rather than simply a rendering problem.

This talk demonstrates how modern C++ atomics can be used to build a lock-free timer scheduler optimized for extremely high update rates. The scheduler follows a single-producer, multiple-consumer design in which work items represent recurring tasks that must execute periodically. Consumers process scheduled work and re-schedule it for future execution without relying on traditional locks or centralized coordination.

The most unusual aspect of the design is its “reverse work stealing” behavior: consumers can proactively give away work to other consumers and become idle themselves. Rather than distributing work evenly across all threads, the scheduler attempts to pack work onto as few cores as possible, reducing idle spinning, lowering CPU utilization, and improving cache locality. Because tasks may have highly variable execution times, the scheduler must also prevent pathological cases where work is endlessly redistributed between consumers.

Attendees will learn how atomics, lock-free forward lists, and memory ordering can be combined to implement high-throughput schedulers with predictable latency characteristics. The talk also discusses practical tradeoffs, implementation challenges, and performance measurements from production-inspired workloads, including producer throughput of approximately 50 million scheduled tasks per second and consumer processing throughput approaching 700 million tasks per second, while keeping migrated work items below 1% in typical workloads.

Presenters
MG

Maxim Gurschi

Maxim Gurschi is a senior software engineer on the FXGO team at Bloomberg, where he is focused on building scalable, high-performance trading systems for electronic foreign exchange trading. In this role, he explores practical applications of modern C++ (20 and above) in latency-sensitive... Read More →
Tuesday September 15, 2026 15:15 - 16:15 MDT
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15:15 MDT

Compile-Time Polymorphism for Runtime-Flexible Systems: Lessons from OpenJDK
Tuesday September 15, 2026 15:15 - 16:15 MDT
Your system has interchangeable strategies chosen at runtime, but the hot path runs millions of times per second. Runtime polymorphism has virtual dispatch overhead. Templates give you performance but lock you at compile time.

This workshop shows how to leverage inheritance for extensibility while avoiding vtable overhead, using a layered architecture of compile-time patterns. We'll build them up through OpenJDK's GC barrier system, where different GC algorithms compose different barriers on one of the hottest paths in the JVM.

We will also discuss trade-offs against alternatives like std::variant, function pointers, and plain virtual dispatch throughout. No JVM knowledge required.

Presenters
avatar for Shubhankar Gambhir

Shubhankar Gambhir

Software engineer, Azul systems
Shubhankar Gambhir is a Software Development Engineer at Azul Systems, where he works on JVM runtime efficiency and warmup technologies. Previously, he contributed to the garbage collector, with a focus on performance and scalability. He enjoys building C++ prototypes to explore systems... Read More →
Tuesday September 15, 2026 15:15 - 16:15 MDT
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16:45 MDT

Practical HPC — Forcing the Compiler's Hand with Modern C++
Tuesday September 15, 2026 16:45 - 17:45 MDT
Practical HPC — Forcing the Compiler's Hand with Modern C++

Achieving near-peak FLOPs on modern CPUs requires exploiting SIMD, register files, and cache hierarchies — yet the levers that matter most (loop unrolling, vectorization width, tile sizes, register tiling) are largely outside the programmer's direct control. Autovectorization is fragile, #pragma unroll is advisory and non-portable, and the information the compiler needs most — loop bounds, problem shapes, working-set sizes — is typically only available at runtime. The result is a familiar gap between theoretical peak and delivered performance, bridged in practice only by hand-written intrinsics or inline assembly, fragile macro forests, or external code generators that sacrifice maintainability and type safety.

Modern C++ is, sometimes surprisingly, an excellent language for closing that gap without leaving the host language. We walk through the concrete features that make this possible and how to use them in practice — templates and constexpr to promote runtime values into compile-time constants, if constexpr and parameter packs for shape-specialized kernels, generic and template lambdas for loop bodies that are unrolled and inlined by construction, and concepts to turn silent performance cliffs into compile-time errors. Together, these give the programmer precise control over what the compiler emits: compile-time dispatch that specializes kernels per shape and target, guaranteed static unrolling that unlocks ILP and register tiling without relying on optimizer heuristics, and hardware-aware specialization parameterized on register count, SIMD width, and cache sizes.

Looking forward, C++26 and static reflection push this approach considerably further, turning today's disciplined metaprogramming into something closer to first-class, in-language code generation — and squarely aligning the language with the goal of making inline assembly unnecessary, even at the highest performance tiers.

These patterns are powerful but verbose and reappear across kernels, so we briefly introduce POET (Performance Optimized Excessive Templates), a header-only library usable from C++17 onward that packages the most common cases as ready-to-use building blocks, alongside xsimd for portable SIMD.

As a concrete case study, we walk through a real scientific-computing kernel — a workload of the kind that has historically demanded hand-tuned assembly — and show how these abstractions get within a small fraction of theoretical peak throughput while keeping the source readable, portable, and maintainable, with no inline assembly, no compiler builtins, and no external code-generation step. Scientific computing does not have to choose between performance and engineering quality, and with the right abstractions, development becomes dramatically more effective.

Presenters
avatar for Marco Barbone

Marco Barbone

Software Engineer, Simons Foundation
Tuesday September 15, 2026 16:45 - 17:45 MDT
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Wednesday, September 16
 

09:00 MDT

Deterministic Storage: Building a Predictable Embedded File System in Modern C++
Wednesday September 16, 2026 09:00 - 10:00 MDT
Embedded systems often operate under strict timing and reliability constraints, yet most existing file systems prioritize throughput and flexibility over predictability. This mismatch can lead to non-deterministic behavior, unbounded latency, and difficult-to-debug failures in resource-constrained environments. In resource-constrained environments such as automotive control units and aerospace flight systems.

This talk explores the design and implementation of a deterministic file system built specifically for embedded systems using modern C++. Rather than focusing on feature completeness, the system prioritizes predictable behavior through fixed block allocation, metadata-first layouts, and bounded operation times.

We will examine how determinism can be treated as a first-class design constraint, influencing everything from on-disk structure to API design. The talk will also highlight how modern C++ features—such as strong typing, RAII, and compile-time configuration—can be leveraged to enforce correctness and reduce runtime overhead without sacrificing clarity.

Attendees will gain insight into real-world tradeoffs required to achieve determinism, including limitations in flexibility and storage efficiency, as well as strategies for adapting the design across different hardware backends such as file-backed devices, SPI flash, and embedded Linux block devices.

This session is aimed at engineers building systems where predictability matters more than peak performance, and who want to apply modern C++ techniques to low-level, resource-constrained environments.

Presenters
ED

Elbert Dockery

Elbert Dockery is a software engineer, worked at several aerospace and defense companies as well as small startups. He has experience with systems software as well embedded systems.
Wednesday September 16, 2026 09:00 - 10:00 MDT
_5

09:00 MDT

Turbocharging Native Code Performance: Compiler Optimizations, Profile-guided Optimizations, and Beyond
Wednesday September 16, 2026 09:00 - 10:00 MDT
Making native code fast is a team sport: efficient algorithms, high-performance libraries, memory-conscious design, and modern hardware all play a role. But the critical link between your code and the hardware it runs on is the optimizing compiler.

This talk explores new & improved compiler optimizations in Visual Studio 2026, and how these improve the performance of existing C++ code with minimal source changes. We will examine both architecture-independent optimizations (such as improved scalar replacement, vectorization, and loop transformations) and architecture-specific enhancements (such as AVX-512 and NEON specific optimizations). Along the way, we will connect high-level C++ constructs to the generated assembly and CPU behavior to build an intuition for how performance improvements are realized. While the talk discusses Visual Studio code generation & optimizations, the tools and analysis apply to all native platforms & compilers.

We will also introduce sample-based profile-guided optimizations (SPGO) which uses the runtime characteristics of your application to guide optimization decisions, WITHOUT requiring traditional instrumentation. You will learn how SPGO works, how to apply it in practice, and where it delivers measurable gains: typically in the 5-15% range across real world native codebases.

Attendees will leave with a practical understanding of how to reason about native code performance, and how to leverage SPGO to turbocharge the performance of their code.

Presenters
EB

Eric Brumer

Eric is an engineering manager on the Microsoft C++ Team, working on the compiler back-end.
Wednesday September 16, 2026 09:00 - 10:00 MDT
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09:00 MDT

Awaiters and Awaitables
Wednesday September 16, 2026 09:00 - 10:00 MDT
C++20 coroutines come with a reputation for complexity — and writing your own coroutine return type deserves that reputation. But here is the good news: you probably don't have to. With std::generator in C++23, high-quality libraries like Asio and cppcoro today, and std::task on its way in C++26, most developers can simply write co_await and move on.

There is one gap, however. Sooner or later, every developer using coroutines needs to bridge an existing asynchronous interface — a timer, an I/O operation, a thread pool callback, a legacy future — into the coroutine world. That bridge is built with awaiters and awaitables, and that is exactly what this session teaches.

We will start from first principles: what does co await actually do? We will demystify the three functions that form the awaiter protocol — await ready, await suspend, and await resume — and build a clear mental model for each. We will implement a real awaiter from scratch, then explore how symmetric control transfer keeps the call stack flat across deeply chained async operations. Next, we will learn how to make any existing type co await-able without modifying it, using operator co await, and how await transform lets you restrict or adapt awaitable behavior to a specific coroutine context. Finally, we will look at how to write cancellation-aware awaiters using std::stop token, so your coroutines respond promptly when work is no longer needed.

No prior coroutines experience is assumed. If you know what co await looks like on the surface but not what happens underneath it, this session is for you. You will leave with both the knowledge and the code to wrap any asynchronous operation into a first-class co await expression.

Presenters
avatar for Mateusz Pusz

Mateusz Pusz

C++ Trainer | Principal Engineer, Train IT | Epam Systems
A software architect, principal engineer, and security champion with over 20 years of experience designing, writing, and maintaining C++ code for fun and a living. A trainer with over 15 years of C++ teaching experience, a consultant, a conference speaker, and an evangelist. His main... Read More →
Wednesday September 16, 2026 09:00 - 10:00 MDT
_2

09:00 MDT

CUDA Tile C++: Practical Automatic Parallelization for the GPU
Wednesday September 16, 2026 09:00 - 10:00 MDT
CUDA Tile C++ is a novel C++ DSL and compiler that automatically parallelizes array operations across GPU threads while presenting a single logical thread to the programmer. In CUDA Tile C++, parallelism is expressed through SIMD-style operations on arrays of data called "tiles" while memory accesses are written using structured memory abstractions. The compiler analyzes the tile and memory operations to generate an equivalent multi-threaded program that leverages the advanced hardware capabilities of modern GPUs. This allows the user to write simple programs that exploit GPU parallelism without needing to manage low level hardware concurrency.

As GPU architectures evolve to meet the demands of high performance computing, the traditional multi-threaded GPU programming model becomes increasingly unwieldy. To achieve optimal performance, the GPU programmer must manage a growing variety of hardware features including shared memory, Tensor Memory Accelerators, and Tensor Cores. Traditional CUDA code is deeply coupled to the underlying hardware resulting in complex and non-portable algorithms. The CUDA Tile C++ compiler removes the need for coordinating these low level hardware details, freeing the user to reason about their algorithm rather than asynchronous code.

The tile programming model introduces three key abstractions:

  • cuda::tiles::tile - a multi-dimensional array with value semantics whose operations are parallelized across the GPU
  • cuda::tiles::tensor_span - a view into a multi-dimensional in-memory array with an interface similar to std::mdspan
  • Tile Views - adapters that present a uniform "chunking" of a tensor_span which gives the compiler visibility into memory access patterns
In this talk, we will explore how these abstractions allow NVIDIA's Tile C++ compiler to schedule the program across hardware threads all while preserving the illusion of a single-threaded abstract machine to the user.

Presenters
ES

Ezra Stein

Ezra Stein is a Senior Compiler Engineer working on NVIDIA's CUDA C++ Frontend team. Since joining the company in 2025, Ezra has focused primarily on the design and implementation of CUDA Tile C++. Prior to working at NVIDIA, Ezra spent 5 years developing MATLAB to C++ source-to-source... Read More →
Wednesday September 16, 2026 09:00 - 10:00 MDT
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09:00 MDT

Ranges Without Compromise: Designing for Simplicity, Performance, and Composability
Wednesday September 16, 2026 09:00 - 10:00 MDT
Range views enable a “no raw loops” style of programming — not as a matter of taste, but as a pragmatic way to reuse well-tested algorithms to write code faster, express intent clearly, and avoid common bugs. In practice, however, developers often run into issues that may lead them to abandon ranges altogether:

  • unintuitive behavior and surprising limitations
  • slower compilation and runtime performance compared to raw loops
  • high complexity when implementing custom views
In this talk, we’ll distill the core design choices behind these problems — and the alternatives that avoid them. In particular, we’ll compare:

  • iterators and indices
  • external and internal iteration
  • transformations of nested views that overcome limitations of internal iteration
Attendees will leave with practical insights for designing and using range abstractions, along with examples of libraries that embody these ideas.

Presenters
avatar for Oleksandr Bacherikov

Oleksandr Bacherikov

Software Engineer
Oleksandr Bacherikov is a software engineer with over a decade of experience building low-latency machine learning and computer vision systems for mobile devices and AR glasses. He is particularly interested in designing abstractions that make complex algorithms simple, efficient... Read More →
Wednesday September 16, 2026 09:00 - 10:00 MDT
_3

14:00 MDT

In Pursuit of a 6,000 FPS Game Boy Emulator
Wednesday September 16, 2026 14:00 - 15:00 MDT
How far can modern C++ push an emulator before performance stops being a C++ problem and becomes a systems problem? This talk is the final part of a CppCon trilogy about building an extremely fast Game Boy emulator in modern C++, moving from high-performance emulation techniques to the limits imposed by hardware, compilers, and CPU architecture.

The target is intentionally absurd but not arbitrary: a Game Boy emulator running Tetris at roughly 100 times original speed, about 6,000 frames per second. However, the goal is not to support every Game Boy cartridge ever made. This project deliberately specializes for one iconic game first, using the code paths Tetris actually exercises as a guide, while keeping enough design discipline to test other games later. That means questioning the architecture of the emulator itself: instruction dispatch, memory access, generated code size, cache behavior, branch prediction, compile-time computation, benchmarking methodology, and the tension between accuracy, maintainability, flexibility, and raw throughput.

This is not a victory-lap performance talk. It is a measurement-driven engineering investigation. Rather than treating 6,000 FPS as just a headline number, this talk treats it as a stress test: a way to force difficult design decisions into the open. Attendees will leave with concrete lessons about performance-oriented C++: how to measure methodically, how to specialize without losing control, how to reason about modern CPU behavior, and how to decide when an optimization is worth its cost.

Presenters
avatar for Tom Tesch

Tom Tesch

Lecturer, DAE - Howest
Tom is currently a senior lecturer for the Bachelor in Digital Arts and Entertainment at Howest University of Applied Sciences, where he is on a mission to inspire the next generation of game developers. His expertise revolves around teaching C++, algorithms, and the core principles... Read More →
Wednesday September 16, 2026 14:00 - 15:00 MDT
_5

14:00 MDT

Interesting Upcoming Low-Latency, Networking, Concurrency, and Parallelism Features from Kona 2025, Croydon 2026, and Brno 2026
Wednesday September 16, 2026 14:00 - 15:00 MDT
This talk is the 2026 edition of our series that highlights low-latency, networking, parallelism, and concurrency proposals to the C++ Standards Committee, especially those discussed in the Kona 2025, Croydon 2026, and Brno 2026 meetings. This talk from the Concurrency TS2 Editors, DG and SG14/19 chair will describe the following features and show how they can be used. It will also give their motivation, background, and their place within the overall framework of C++ low latency, networking, parallelism and concurrency:

Atomic Compare and Hazard Pointers Reclamation Control

  • We discuss a proposal for atomic compare operations that clarify programmer intent and simplify static analysis by avoiding the unnecessary leakage of atomic values. We also explore how these operations complement recent proposals to enhance the expressiveness of atomics, such as the use of tagged pointers.
  • We examine techniques for controlling C++26 hazard pointer reclamation, demonstrating how to offload retirement overhead to asynchronous executors to ensure predictable thread latency. We show how this capability can prevent specific deadlock scenarios and assess whether such controllers should be standardized or remain user-space patterns.
Twenty-One Years Without Sockets, The History of Networking in C++ and What We Learned Along the Way

  • Go has standard networking. Rust has standard networking. C++ has been trying since 2005. This talk tells the twenty-one-year story in seventeen minutes: the library that shipped but never standardized, the dependency that blocked it, the coroutine revolution that changed the assumptions, the technical discovery that explains why I/O doesn‚Äôt fit the three-channel model cleanly, and the bridge that lets both models win. Three decision points, three lessons, one live question: how should coroutines and senders coexist for C++29? No villains. Just the story and the engineering. Networking is now finally a C++29 priority, so said the Direction Group‚Äôs P5000.
Out-of-Thin-Air (OOTA) Values.

  • The memory models for high-level languages, including C++, C, Rust, and even Java, have been prone to out-of-thin-air values. For example, given two atomic integers X and Y, both initially zero, if one thread does a relaxed assignment from X to Y and the other does a relaxed assignment from Y to X, the mathematical C++ memory model does not rule out the outcome where both X and Y have the value 42. However, both communication and computation take time, and so we have proven that OOTA values cannot happen on real-world production-quality computer systems. This result makes compiler-writers‚Äô lives easier, and also eases the jobs of those brave individuals pursuing the full mathematical OOTA problem by relieving them of the need to live within CPU and memory constraints of production-quality compilers.
Discussion

There are other features under discussion, but the features we will present seem close to approval, are particularly interesting, and/or are relatively non-controversial. We will show use cases for each and prognosticate their journeys to C++26 and beyond. This will help programmers in concurrency, lock-free programming, and low-latency applications understand how best to take advantage of each of these important facilities.

Presenters
avatar for Paul E. McKenney

Paul E. McKenney

Software Engineer, Facebook
Paul E. McKenney has been coding for almost four decades, more than half of that on parallel hardware, where his work has earned him a reputation among some as a flaming heretic. Paul maintains the RCU implementation within the Linux kernel, where the variety of workloads present... Read More →
avatar for Maged Michael

Maged Michael

Staff Software Engineer, Category Labs
Maged Michael is the inventor of several concurrent algorithms including hazard pointers, lock-free allocation, and multiple concurrent data structure algorithms. His code and algorithms are widely-used in standard libraries and production. His 2002 paper on hazard pointers received... Read More →
avatar for Michael Wong

Michael Wong

CTO, Distinguished Engineer, YetiWare
Michael Wong is the CTO of YetiWare an AI company, and was a Distinguished Engineer/VP of R&D at Codeplay/Intel. He is a current Director and VP of ISOCPP, Chair of the C++ Direction Group, and a 25 year senior member of the C++ Standards Committee with more than 15 years of experience... Read More →
Wednesday September 16, 2026 14:00 - 15:00 MDT
_1

14:00 MDT

The Ghost in the Heap: Defeating a Memory Thief
Wednesday September 16, 2026 14:00 - 15:00 MDT
In the C++ world, it is often assumed that proper object lifetime management ensures a memory footprint that scales with an application’s actual needs. However, long-running systems are frequently sabotaged by heap pinning: a phenomenon in which Resident Set Size (RSS) refuses to shrink even after significant deallocations. This results in a critical, 'invisible' overhead that defies standard leak-detection tools and can lead to system thrashing and even Out Of Memory (OOM) kills.

Heap pinning occurs when long-lived allocations are interleaved with transient ones, creating a structural barrier that prevents the underlying allocator from releasing memory back to the system. A single persistent allocation can 'pin' an entire block of physical memory, forcing the OS to keep it mapped even if the surrounding space is empty. Consequently, the process footprint reflects historical peak usage rather than the current live state.

In this talk, we will bridge the disconnect between C++ deallocations and physical memory reclamation. You will learn to use allocator-aware objects and std::pmr resources to eliminate pinning by strategically segregating allocations based on their expected lifetimes. We will also demonstrate how to diagnose these 'ghost' overheads when traditional heap profilers fall short. You’ll leave the session equipped to identify and resolve these fragmentation traps, ensuring your application’s memory footprint finally stays proportional to its actual state.

Presenters
avatar for Nicolas Arroyo

Nicolas Arroyo

Software Architect, Bloomberg
Nicolas Arroyo has spent two decades crafting C++ in high-stakes environments, spanning VoIP, embedded systems, distributed systems, and low-latency financial infrastructure. Currently, he specializes in building performance-analysis tooling, system-level benchmarking, and eliminating... Read More →
Wednesday September 16, 2026 14:00 - 15:00 MDT
_2

14:00 MDT

Automatic Splitting of Translation Units: Compiler-Agnostic Compiler Frontend Parallelization
Wednesday September 16, 2026 14:00 - 15:00 MDT
AI agents are accelerating code generation at an unprecedented pace, yet C++ file is still compiled as a monolithic translation unit, meaning a many-core machine often cannot rebuild a template-heavy file much faster than a single core. Header-heavy designs, inline functions, and templates compound the problem: the same bodies are parsed repeatedly, and small edits can invalidate an entire translation unit.

This talk presents a compiler-agnostic technique for splitting translation units into smaller independently compilable units. Using libclang, the tool rewrites headers and sources into declaration-only interfaces plus generated .cpp fragments, backed by a shared preamble that can turn into a C++ module, precompiled header, cached serialized AST and a source-map. The fragments compile in parallel, then link into a binary functionally equivalent to the original monolithic build.

Expect benchmarks from major codebases covering compile-time, link-time, and run-time performance; live demos of fast incremental updates that avoid reprocessing unchanged code as well as an analysis of the resulting binaries layout.

Presenters
avatar for Damien Buhl

Damien Buhl

co-founder, tipi.build
Damien (aka daminetreg), co-founder tipi.build by EngFlow is an enthusiast C++ developer. Opensource entrepreneur, CppCon Speaker, GameMaker.fr community founder, Qt for Android contributor and Boost.Fusion maintainer since 2014.
Wednesday September 16, 2026 14:00 - 15:00 MDT
_6

15:15 MDT

Writing High Performance Parsers Using State Machines
Wednesday September 16, 2026 15:15 - 16:15 MDT
Starting from the simple objective of writing an optimized lexer we will grapple with their fundamental performance factor: branch prediction. We will investigate how lookup tables can improve (or hurt) the CPUs prediction capabilities with some unexpected results. Over time our design evolves by combining parsing and lexing into a single step in a way that is as fast as just a standalone lexer. A central aspect of the design will be a primitive parsing state machine from which the parser source code is generated.

After the talk attendees will have a better understanding of some advanced branch prediction techniques and should have some new ideas for their present or future parsing endeavors.

Presenters
TT

Torben Thaysen

Torben Thaysen was passionate about software from a young age with his earliest C++ experiments dating back over 10 years. After acquiring his masters degree in physics he returned to his passion and became a C++ developer currently with 2 years experience under his belt. Now Torben... Read More →
Wednesday September 16, 2026 15:15 - 16:15 MDT
_1

16:45 MDT

Zero Cost Scripting Languages for Game Engines With C++26 Static Reflection
Wednesday September 16, 2026 16:45 - 17:45 MDT
Scripting in a C++ game engine should not cost you the engine's native performance. This talk shows how C++26 static reflection and std::meta::substitute in particular can lift a scripting language's bytecode into C++ template structures that the compiler optimizes away entirely, collapsing the interpreter dispatch loop into the same machine code you'd write by hand. Scripting languages like AngelScript and Lua are invaluable in C++ engines: they give designers a fast iteration loop without rebuilding the engine. But they come with a paradox. The engine you chose for raw performance now spends cycles on every frame interpreting a slower language, juggling a software stack and checking types at runtime. We will walk through the technique step by step, starting from a plain bytecode interpreter and ending at a fully reflected program where a scripted sum(0..10) compiles to mov eax, 45; ret. Along the way you'll learn the core C++26 reflection primitives (^^, [: :], std::meta::substitute), how to assemble bytecode into structural templates like block<> and loop<>, and how these techniques generalize to embedding any stack or register based scripting language in your engine with zero runtime overhead.

Presenters
avatar for Koen Samyn

Koen Samyn

Koen is a senior software engineer and lecturer at digital art and entertainment whose primary focus is bringing modern C++ to GPU-driven game technology. Over the past decade he has built and optimized compute-shader pipelines for lighting, physics, and inverse kinematics. In the... Read More →
Wednesday September 16, 2026 16:45 - 17:45 MDT
_4

16:45 MDT

Modern C++ Techniques to Reduce Boilerplate Without Sacrificing Performance
Wednesday September 16, 2026 16:45 - 17:45 MDT
Modern C++ gives developers powerful tools to write cleaner, safer, and more expressive code — but many production codebases still suffer from excessive boilerplate, repetitive patterns, and verbose implementations inherited from older C++ styles.

This talk explores practical modern C++ techniques that significantly reduce lines of code while preserving readability, maintainability, and runtime performance.

Through real-world examples, we will refactor traditional C++ implementations using features such as ranges, structured bindings, constexpr, concepts, CTAD, lambdas, std::optional, std::variant, and std::expected. We will examine where these features genuinely improve code quality — and where they can accidentally hurt clarity or performance if misused.

The session also goes beyond syntax improvements by analyzing generated assembly, compiler optimizations, allocations, and benchmark results to validate whether “shorter” code truly remains zero-cost.

Attendees will leave with practical patterns they can immediately apply to modernize existing codebases, reduce unnecessary complexity, and write more expressive C++ without sacrificing performance.

Presenters
avatar for VISHNU G NATH

VISHNU G NATH

Seasoned software developer with over 7 years of experience specializing in modern C++ development across industrial automation, semiconductor manufacturing, and enterprise systems. He currently works as a Technical Lead Software at Applied Materials, where he architects and implements... Read More →
Wednesday September 16, 2026 16:45 - 17:45 MDT
_5
 
Thursday, September 17
 

09:00 MDT

Tying up Loose Threads: Making Your Project No-GIL Ready
Thursday September 17, 2026 09:00 - 09:30 MDT
Python's Global Interpreter Lock, which determines which single thread can execute native Python code and call C API functions, simplifies writing multithreaded code. By default, the most popular C++ bindings to this API, pybind11 and Cython, implicitly enables the GIL by default. However, sticking with this execution model leaves out extra performance afforded by modern multicore CPUs with hyperthreading, as automatic locking and unlocking of the GIL does not scale well with thread counts, especially in performance-sensitive workloads.

The newfangled free-threaded interpreter promises salvation when running either pure Python code or with compiled extensions. General multithreading rules apply (prefer thread-local variables, using locks to prevent simultaneous access of shared data), but when dealing with projects containing compiled extensions that directly or indirectly interface with Python's C API, more porting rules also apply.

Key porting tips, including projects using the Limited API, include: port native code away from C API functions that avoid borrowed references because they aren't thread-safe; modify unit tests to catch concurrency bugs arising from assuming the presence of the GIL; and extend CI coverage of Python interpreters both for testing and to build free-threaded compatible wheels.

Presenters
CL

Charlie Lin

Freelancer, N/A
Thursday September 17, 2026 09:00 - 09:30 MDT
_5

09:00 MDT

Back to Basics: Loops in C++
Thursday September 17, 2026 09:00 - 10:00 MDT
A fundamental control structure of each programming language are loops. And we all expect them to be simple and self explanatory. However, C++ would not be C++, if there would be no tricky details to learn and respect about loops in C++.

This talk takes its time to discuss the various ways and approaches to program loops in C++. Beside basic while and for loops, we talk about the range-based for loop, and all the extensions recently added to these control structures.

In addition, we will look at other ways to program loops in C++, such as using algorithms and how to deal with parallel computing in a loop.

As a result you get a deeper understanding of the various ways loops can be programmed in Modern C++ so that you know better how to use them in practice.

Presenters
Thursday September 17, 2026 09:00 - 10:00 MDT
_3

09:00 MDT

Writing Low-Latency C++: Predictability, Cache, and the Architectures Underneath
Thursday September 17, 2026 09:00 - 10:00 MDT
In low-latency C++, correctness is table stakes. What separates good systems from great ones is predictability — the ability to hit your deadline not just on average, but at the 99th and 99.9th percentile, where real workloads live. Latency is a feature, and if you don't design for it explicitly, you lose it accidentally.

This talk is a practitioner's guide to writing C++ that behaves predictably under load, drawn from experience building and tuning low-latency systems on Microsoft's Azure Core platform. We start from the mental models that matter most — CPU-centric thinking, the latency stack from L1 to DRAM, and why minimizing work, unpredictability, and memory movement is the foundation of everything else — and then work through the layers of the stack where latency is won or lost in practice.

Through live demos and benchmark data on both x86 and ARM, we'll cover:

STL containers as latency contracts — why most latency bugs start with the wrong container, the real cost of dynamic reallocation, and the measurable wins from reserve() and custom allocators.

Memory layout and cache behavior — struct layout and alignment (and how it differs on x86-64 vs. ARM64), AoS vs. SoA trade-offs, hot/cold data separation, false sharing, NUMA, and TLB pressure.

Atomics vs. mutexes — when atomics actually lose to mutexes, why architecture and memory model dictate the answer, and how to choose between them in real code.

Threading and scheduling — fixed vs. dynamic thread pools, context-switch and migration costs, and why understanding the OS is half the battle.

Benchmarking and observability — why microbenchmarks lie, how to avoid measurement bias and jitter, why latency histograms beat averages, and why "absolute benchmark" is a myth.

You'll leave with a practical playbook for designing and measuring low-latency C++ systems, an honest understanding of why benchmarks from one machine rarely generalize to another, and a sharper instinct for the silent killers — allocations, branches, cache misses, and synchronization primitives — that don't show up in code review but do show up in production.

Presenters
avatar for Sampad Acharya

Sampad Acharya

Senior Quant Developer, Fixed Income Trading, Bloomberg
Sampad Acharya is a senior software engineer at Bloomberg, where he specializes in low‑latency, cache‑optimized C++ systems for trading and real‑time environments. He has worked in software development for six years. Sampad is deeply interested in how algorithms behave in the... Read More →
Thursday September 17, 2026 09:00 - 10:00 MDT
_1

09:35 MDT

[[musttail]]-ling Our Way to a Faster Python Interpreter and New JIT Compiler
Thursday September 17, 2026 09:35 - 10:05 MDT
In CPython 3.14, we introduced an alternative interpreter implementation. This implementation used [[musttail]] , an experimental C/C++ feature that tells the compiler to enforce tail calls. Against the previous interpreter using computed gotos/switch-case, the new interpreter style shows 2%--15% performance improvement (i.e. geometric mean running time), and is more resilient against certain types of compiler bugs. This feature is already supported by Clang, GCC, and MSVC, and is also the center of a draft proposal targeting C++29. In this talk, I’ll cover the story of getting this feature into the Python interpreter, our collaboration with compiler developers, and the potential wider impact on the C++ community. I’ll also cover interesting use cases of this feature other than for writing interpreters, such as for automatically generating a simple Just in Time (JIT) compiler.

Presenters
KJ

Ken Jin Ooi

Ken Jin Ooi is a Python maintainer since 2021 and is also currently a contractor for OpenAI. His Python work revolves around the performance of the Python interpreter, which is written in a subset of C11 that is mostly compatible with C++.
Thursday September 17, 2026 09:35 - 10:05 MDT
_5

14:00 MDT

C++ in the Age of AI: How Visual Studio Is Evolving
Thursday September 17, 2026 14:00 - 15:00 MDT
For almost 30 years, Visual Studio has been a core part of the C++ developer's toolkit on Windows. This year, we're building on that foundation with investments across three themes: making the IDE faster and more responsive for large codebases, advancing compiler conformance and runtime performance, and integrating AI-powered workflows that help you debug, refactor, and optimize more effectively. Beyond the IDE, we'll show you how AI-powered command-line tools can become a natural part of your development process. This session combines demos and practical guidance so you can get the most out of these tools right away. Come with curiosity, leave with new techniques you can apply immediately.

Presenters
avatar for David Li

David Li

Game Developer Product Manager, Microsoft
David Li is the Game Developer Product Manager at Visual Studio with 12 years of experience in the software industry. As a gamer himself, David is especially passionate about enhancing game developer productivity through improving tooling for Visual Studio. In his free time, he enjoys... Read More →
avatar for Augustin Popa

Augustin Popa

Senior Product Manager, Microsoft
I am a product manager on the Microsoft C++ team, working on the Visual Studio IDE and vcpkg, the C/C++ package manager.
Thursday September 17, 2026 14:00 - 15:00 MDT
_6

14:00 MDT

Using Modules in a Real Project
Thursday September 17, 2026 14:00 - 15:00 MDT
C++20 modules are finally usable end to end, from your own modules to 'import std;' The functional build-system support with real diagnostics. This talk teaches modules the way #include was once taught: with small files, a build, and concrete use cases. Modules stopped being experimental somewhere around 2025. This session builds the mental model from scratch: what a primary module interface unit is, how partitions and implementation units fit together, and, crucially, how import differs from #include in ways that matter day to day. It uses a small library, exposes it as a module, splits it across partitions, consumes import std; and observes the compile-time effect. Then it answers the questions every team hits in week one: how modules interact with macros, with templates in headers, with header-only dependencies, and with a mixed codebase that can't convert everything at once. The examples will be using CMake, clang and recent gcc. You will leave able to structure a small library as a module, explain why a macro didn't cross a module boundary, and plan an incremental adoption that doesn't require converting the whole tree.

Presenters
avatar for Erez Strauss

Erez Strauss

Strat - Sr Software Engineer, Eisler Captal
Erez Strauss worked in Banks and Hedge Funds while focused on low latency systems.
Thursday September 17, 2026 14:00 - 15:00 MDT
_3

14:00 MDT

When Zero-Cost Abstractions Aren’t Zero-Cost
Thursday September 17, 2026 14:00 - 15:00 MDT
Zero-cost abstractions are a foundational idea in C++, promising expressive, high-level code without sacrificing performance. However, developers often encounter unexpected costs when using modern abstractions in practice, even when the code appears idiomatic and well-designed.

This talk explores the assumptions behind zero-cost abstractions and examines what happens when those assumptions no longer hold. Through concrete examples drawn from modern C++ — including ranges and views, type erasure, allocators, and other common abstractions — we will examine how factors such as optimizer visibility, inlining boundaries, allocation behavior, and runtime flexibility influence performance.

This talk treats abstraction as a powerful engineering tool, examining the limits of its zero-cost guarantees in real-world systems. We will look at how seemingly small design choices can introduce hidden costs, why those costs are often difficult to spot through inspection alone, and how to recover performance without abandoning good design or readability.

Attendees will leave with a clearer understanding of when abstractions are truly zero-cost, how to recognize situations where they are not, and how to make informed tradeoffs between expressiveness, flexibility, and performance in modern C++.

Presenters
avatar for Steve Sorkin

Steve Sorkin

Senior Software Engineer, Bloomberg
Steve Sorkin has been at Bloomberg since 2019, where he is a senior software engineer. He is enthusiastic about writing clean, scalable, and maintainable code for use in low latency and high throughput applications. Prior to joining Bloomberg, Steve worked as a securities/derivatives... Read More →
Thursday September 17, 2026 14:00 - 15:00 MDT
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15:15 MDT

Leveraging LLM to Generate Unittests for Notifiers in Taskflow
Thursday September 17, 2026 15:15 - 16:15 MDT
Notifiers are a critical synchronization primitive in task-parallel programming systems such as Intel TBB and Taskflow, responsible for efficiently sleeping and waking worker threads as tasks become unavailable and available over and over again, directly impacting scheduler throughput and latency. Correctness here is non-negotiable: a single missed wakeup can significantly hamper the performance of an entire program. Yet writing strong unit tests for notifiers is notoriously difficult, because the bugs they target, lost wakeups, spurious wakes, race conditions, are timing-dependent, non-deterministic, and often only surface under specific thread interleavings that are hard to force reliably.

The problem is compounded in practice. Notifier implementations evolve constantly: small algorithmic tweaks, memory ordering changes, and refactors across systems demand a fresh round of carefully constructed tests. This is tedious, expertise-heavy work that takes a lot of time and engineering effort. In this talk, we explore using Large Language Models (LLMs) to automate the generation of the unit tests for notifiers. Specifically, we will demonstrate how LLM-generated tests, guided by proper prompts can systematically stress the two-phase wait protocol across Notifiers in Taskflow. We will show this in a widely used Notifier implemented in Taskflow. We are able to find an undiscovered bug that has been existing in the project.

Presenters
SS

Snikitha Siddavatam

Snikitha Siddavatam is a Computer Science and Data Science student at the University of Wisconsin-Madison, expected to graduate in May 2027, with coursework spanning machine learning, artificial intelligence, distributed systems, data visualization, and advanced algorithms. Snikitha... Read More →
Thursday September 17, 2026 15:15 - 16:15 MDT
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15:15 MDT

The Latency Slippage: Understanding the Hidden Costs of Caching for Low Latency C++
Thursday September 17, 2026 15:15 - 16:15 MDT
Choosing cache-friendly data structures is a well-known optimization, but it's rarely the whole story. This talk goes deeper, exploring the hardware mechanics that dictate real-world performance and showing where significant gains are still left on the table.

We'll start from the ground up: what actually happens inside the cache hierarchy when your code issues a memory read or a software prefetch? Understanding the hardware lets us answer, when you should prefetch manually, and when you should trust the hardware prefetcher.

From there, we'll examine the invisible cost of multi-core C++. Cache coherency protocols (MESI/MOESI) can silently degrade performance through false sharing, RFO stalls, and coherency storms. We'll walk through how to diagnose these issues using hardware performance counters and how to eliminate them.

Additionally, we will contrast these behaviors across the data cache (DCache) and instruction cache (ICache), and analyze how Translation Lookaside Buffers (TLBs) impact overall memory read latency.

Finally, we'll tie it all together by combining hardware insight with application profiling data to arrive at practical strategies for low latency C++, packaged as an application-aware memory allocator.

Presenters
SG

Sanchit Gupta

Sanchit Gupta graduated from Indian Institute of Technology, Madras with Honours in Bachelors of Technology in Computer Science and Engineering. Since graduating, Sanchit has worked for Graviton as a Low latency Software Developer
Thursday September 17, 2026 15:15 - 16:15 MDT
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16:45 MDT

Extending Google Test for Statistical Benchmarking, CUDA Profiling, and CI Performance Regression
Thursday September 17, 2026 16:45 - 17:15 MDT
Benchmarks shouldn't live in a different world from tests. Most C++ projects already use Google Test, but the moment performance enters the picture, developers reach for separate tools, separate workflows, and ad-hoc timing loops that don't survive contact with CI. This talk argues for a different default: treat performance measurements as first-class tests. They are written in the same harness, run in the same suite, and fail the same builds.

Using a real C++23 framework built on top of Google Test, the session shows what that looks like in practice. Semantic macros distinguish throughput, latency, and contention tests; built-in statistical analysis tracks medians, percentiles, and coefficient of variation. Adaptive thresholds scale with payload size, so tiny operations and multi-megabyte workloads aren't held to the same stability expectations.

Once benchmarking lives inside the test framework, the rest of the performance toolchain follows. Five CPU profiler backends drop in behind a single --profile flag: perf, gperftools, bpftrace, RAPL, and callgrind. Attaching a memory profile to a test prints bandwidth, efficiency, and a CPU-bound or memory-bound classification with no extra code. The same harness extends to CUDA through a fluent kernel builder that captures launch configuration, achieved occupancy, transfer overhead, multi-GPU scaling efficiency, and thermal throttling. Nsight Compute drops in through the same --profile flag.

The payoff is CI integration that's nearly automatic. A companion CLI tool compares baseline and candidate runs, applies statistical thresholds, posts markdown reports on pull requests, and fails the build on regressions. The result is a single workflow for performance verification that scales from a developer's laptop to a CI runner to a Jetson on a workbench, across hardware ranging from x86 to ARM to RISC-V.

Presenters
Thursday September 17, 2026 16:45 - 17:15 MDT
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16:45 MDT

Are You Smarter Than A Branch Predictor?
Thursday September 17, 2026 16:45 - 17:45 MDT
Are you smarter than a branch predictor? In this interactive, game-show themed session, the audience becomes the branch predictor: participants vote on which of two C++ snippets will run faster before we examine what actually happens on real hardware. The snippets are drawn from real world production code, and correct answers are rewarded with stress balls. Through these examples, we build a practical mental model of how modern CPUs handle control flow, and why even small branching decisions can have a significant impact on performance. A single mispredicted branch can stall a CPU pipeline for dozens of cycles, making control flow a hidden bottleneck in performance-critical systems. Using annotated assembly, performance counter data, and cross-platform comparisons, this talk explores branch prediction, misprediction costs, indirect calls and virtual dispatch, and the trade-offs between branches and conditional moves. We examine how compilers (GCC, Clang, MSVC) transform code under different optimization levels (such as -O2 and -O3), and highlight non-obvious cases where “branchless” code performs worse or behaves differently across architectures. The examples are intentionally small micro-benchmarks, but each exposes patterns that appear in real-world systems when control flow becomes the bottleneck. The session also covers how to design trustworthy micro-benchmarks and validate performance changes using hardware counters. Attendees will leave with a clearer understanding of how branches behave on modern processors, when to rely on compiler optimizations, and when to measure and optimize manually.

Presenters
avatar for Michelle D'Souza

Michelle D'Souza

Software Engineer, Bloomberg
Michelle Fae D’Souza is a Software Engineer at Bloomberg, where she develops C++ code for the company’s order-trade entry and modification (OTE API) solution, which streamlines trading activity for many firms in the financial world. She is an active member of Bloomberg's C++ Guild... Read More →
Thursday September 17, 2026 16:45 - 17:45 MDT
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16:45 MDT

Quicker Than Quick: Using Radix Sort to Make `std::stable_sort` Beat `std::sort`
Thursday September 17, 2026 16:45 - 17:45 MDT
This talk takes you through the research and optimization of radix sort, culminating in its integration into libc++.

You will learn : common pitfalls of radix sort implementations (non-binary digits, dynamic memory allocation, fragile interfaces), how to design a strict and high-performance interface (fixed digit size, external buffer, projection to integers), and how to overcome radix sort's main drawback — its lack of naturalness — with two counter-based optimizations and a hybrid merge scheme.

The result : on arrays of 60 int32 elements (18 for int8), radix sort starts beating std::sort ; on large arrays, it's up to 10x faster. Floating-point types (float/double/float16_t) are also supported via IEEE 754 bit transformations (sign and exponent inversion for negative numbers).

The key takeaway : in modern libc++, for integers and floats, std::stable_sort on random data is noticeably faster than std::sort . Life has become better, but also more complicated — choose your sorting algorithm wisely.

Presenters
DI

Dmitriy Izvolov

C++ Developer
Dmitry Izvolov graduated from MIEM (Moscow Institute of Electronics and Mathematics) with a degree in Applied Mathematics. Since then, he has worked as a programmer across diverse domains: DLP systems, information retrieval, cybersecurity, image processing, and speech synthesis. Currently... Read More →
Thursday September 17, 2026 16:45 - 17:45 MDT
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Friday, September 18
 

09:00 MDT

“If You Can’t Measure It, You Can’t Improve It”: From Profiling to Automatic Benchmarking
Friday September 18, 2026 09:00 - 10:00 MDT
Modern hardware is increasingly complex and difficult to reason about; effective C++ performance work therefore demands a disciplined loop - profile, benchmark, analyze. Yet profiling alone is tricky, doesn’t answer “what if” questions, and manual benchmarking is dominated by hidden biases.

This talk presents a novel automatic benchmarking approach that focuses on eliminating measurement biases. We combine symbolic execution of identified hot regions with microarchitectural state randomization to systematically explore latency and throughput behavior under diverse - cache, branch, data layout - conditions. The technique is integrated with Linux perf, so the entire process - region isolation, state variation, measurement, analysis - is fully automatic.

The talk first grounds attendees in profiling with hardware performance counters, Top‑down Microarchitecture Analysis (TMA), and processor tracing. We then demonstrate how to automatically stress specific microarchitectural features to produce statistically reliable, "bias‑free" benchmarks. Finally, we close the loop with machine‑code analysis, showing how the measured numbers connect directly to instruction‑level behavior and ultimately to C++ code.

Attendees will leave with a concrete framework they can apply immediately to better understand and improve C++ performance.

Presenters
avatar for Kris Jusiak

Kris Jusiak

Lead Software Engineer, Citadel Securities
Nanosecond count
Friday September 18, 2026 09:00 - 10:00 MDT
_5

09:00 MDT

C++ Views and Pipelines
Friday September 18, 2026 09:00 - 10:00 MDT
C++ Views were introduced with C++20 and extended with C++23 and C++26. They are lightweight objects that specify how to use (specific) elements of collections and their values. By composed into pipelines, programmers can easily define complex processing of collections of data.

However, the use of views also has pitfalls and traps. Therefore you should know about * The consequences of reference semantics * The problems of caching Views * The problems of using const with views * The Filter View Fiasco

This talk gives an overview about both the technology and where to pay special attention.

Presenters
Friday September 18, 2026 09:00 - 10:00 MDT
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10:30 MDT

Back to Basics: Containers
Friday September 18, 2026 10:30 - 11:30 MDT
How to Choose and Use the Right Container in Modern C++: Part 1, Classic Containers

Choosing the right container and using it correctly can have a profound impact on the performance of a program, but doing so is harder than you might think. In Part 1 we will survey the containers and adaptors in the C++17 Standard Library, and discuss how to choose the best tool for the job and extract the best performance from it. We will consider the abstractions they model and the practical limitations they impose, and find that choosing between them requires an understanding not only of the speed and size tradeoffs of each container, but also of the difference between algorithmic complexity and actual behavior. And we will flag aspects of the standard containers that, without this understanding, can lead you to the wrong choice.

How to Choose and Use the Right Container in Modern C++: Part 2, New and Future Containers

Choosing the right container and using it correctly can have a profound impact on the performance of a program, but doing so is harder than you might think. In Part 2 we will survey the new containers and adaptors introduced to the Standard Library in C++23/26, and discuss how to choose the best tool for the job and extract the best performance from it. We will consider the abstractions they model and the practical limitations they impose, and find that choosing between them requires an understanding not only of the speed and size tradeoffs of each container, but also of the difference between algorithmic complexity and actual behavior. And we will examine a proposal for a future container that diverges from the historical STL design principles and ask: what makes for a good container design?

Presenters
avatar for Alan Talbot

Alan Talbot

Manager - Software Engineering, LTK Engineering Services
Alan Talbot started programming in 1972, in BASIC on a DEC PDP-8. He began his professional programming career in 1979 and started using C++ in 1989. For 20 years he was a pioneer in music typography software, then spent 8 years writing digital mapping software, and has spent the... Read More →
Friday September 18, 2026 10:30 - 11:30 MDT
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10:30 MDT

IEEE 754 Decimals for C++: The Boost.Decimal Library
Friday September 18, 2026 10:30 - 11:30 MDT
Why does 0.1 + 0.2 not equal 0.3? Because binary floating-point cannot exactly represent most decimal fractions, the value 0.1 simply does not exist in IEEE 754 binary. For applications where rounding errors are unacceptable, finance, billing, regulatory reporting, scientific data interchange, this is a structural problem, not a precision setting that can be tuned away. IEEE 754-2008 introduced a decimal floating-point alternative that stores the significand in base 10, and ISO/IEC TR 24733 sketched a C++ binding for it. Compiler support, however, has remained uneven across vendors and architectures.

Boost.Decimal is a header-only, dependency-free, C++14 implementation of IEEE 754-2008 and TR 24733 decimal floating-point. It provides three IEEE-conformant types, decimal32 t, decimal64 t, and decimal128 t, and three companion decimal fast* t types that trade strict bit-layout conformance for speed where you don't need on-the-wire interoperability. All six types behave like built-in floating-point: they're constexpr-friendly throughout, support mixed arithmetic and promotion, and ship with their own implementations of , , , , , hashing, , and Boost.Math integration. The library is tested natively on x86 64, ARM64, and s390x, and under emulation on PPC64LE and ARM Cortex-M.

This talk is the introduction to decimal floating-point that most C++ programmers never got. We'll cover what decimal floating-point actually is at the bit level (BID vs. DPD encodings, the cohort concept that has no analogue in binary), why the standard library's defaults are what they are (e.g. Rounding), and how Boost.Decimal's API maps onto familiar and patterns. We'll work through worked examples, parsing a price feed, computing financial summary statistics through Boost.Math, round-tripping values through while preserving cohort information, and walk through the library's deliberate deviations from both IEEE 754 and the C++ standard, including why floating-point exception flags were sacrificed to keep constexpr and how from_chars was extended to distinguish overflow from underflow as well as preserve cohorts. We'll close with reviews of the benchmarks versus binary floating point, as well as other existing libraries.

By the end, attendees will know when reaching for decimal is the right call, which of the six types fits their workload, and what trade-offs the library made on their behalf.

Presenters
avatar for Matt Borland

Matt Borland

Staff Engineer, The C++ Alliance
Matt Borland earned his bachelor's from the University of Michigan and his master's from the Georgia Institute of Technology, and is currently a doctoral candidate in Electrical and Computer Engineering at Purdue University. He is the author of Boost.Charconv and Boost.Decimal, both... Read More →
Friday September 18, 2026 10:30 - 11:30 MDT
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13:30 MDT

Back to Basics: Text Formatting
Friday September 18, 2026 13:30 - 14:30 MDT
Most C++ programmers are familiar with the traditional C++ facilities for text processing found in the iostream and string libraries. However, std::format (C++20) and std::print (C++23) provide new text formatting tools that are unfamiliar to many C++ programmers. While these new facilities can be very helpful, they can also produce some very intimidating error messages when misused. Moreover, the process for writing your own user-defined types that you can format with std::format and std::print is not very straightforward.

This session starts with an overview of the traditional C and C++ text processing libraries. It then shows how std::format and std::print neatly combine benefits from both the C and C++ libraries to create a safer, more convenient interface. After that, this session explains the steps you must take to write user-defined types that work cleanly with std::format and std::print. You’ll leave this session with a clearer understanding of the benefits of using these new text formatting facilities and how to integrate them into your existing code base.

Presenters
avatar for Ben Saks

Ben Saks

Chief Engineer, Ben Saks Consulting
Ben Saks is the chief engineer of Saks & Associates, which offers training and consulting in C and C++ and their use in developing embedded systems. Ben has represented Saks & Associates on the ISO C++ Standards committee as well as two of the committee’s study groups: SG14 (low-latency... Read More →
Friday September 18, 2026 13:30 - 14:30 MDT
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14:45 MDT

Our Journey Toward a Fully Backward-Compatible, UB-Safe, ISO C++
Friday September 18, 2026 14:45 - 15:45 MDT
Today's world runs on C++. That's because, in domains requiring scale, performance, low latency, and fine-grained control over concurrency, C++ is second to none! Yet in recent years, a growing concern has emerged: C++ programs are often considered unsafe — not because of programmer negligence, but because the language itself provides insufficient mechanisms to prevent or reliably detect undefined behavior (UB).

For those financially and technically invested in C++, its current lack of language safety raises a fundamental question: How can we evolve ISO C++ to be UB-safe without necessarily sacrificing runtime performance, and without breaking backward compatibility with existing, valid C++ code?

In this talk, we begin by motivating an overall approach to UB-safety that starts from a simple but uncompromising premise: each individual potential source of UB must be able to be detected via runtime checking. Crucially, this approach eliminates the notion of "safe" and "unsafe" regions of a program — there is no place where UB can hide, and no need to switch languages, subsets, or tools to achieve comprehensive coverage.

We then examine how the C++26 contracts facility provides the essential foundation for transforming optional runtime checks into the practical, scalable mechanisms to eliminate UB bugs in production software. Contracts give developers fine-grained control over where and when checking occurs, allowing runtime overhead to be spent where it is affordable or most valuable — such as in new, rarely executed, or security-critical code. These decisions naturally evolve over time, as long-running checks that never fire may no longer justify their cost.

Finally, we outline the concrete steps of an incremental journey toward reducing undefined behavior in ISO C++. The result is a model of UB-safety — rooted in C++26 contracts and optional runtime checking — that is competitive with, and in key respects stronger than, approaches taken by other high-performance languages. Most importantly, this model applies not only to new code, but to the vast body of existing C++ software already in the wild.

Presenters
JL

John Lakos

John Lakos, author of Large-Scale C++ Software Design (Pearson, 1996), is currently exploring the application of AI to large-scale C++ software design. From 2001 to 2026, he served at Bloomberg LP in New York City as a senior architect and mentor for C++ Software Development worldwide... Read More →
Friday September 18, 2026 14:45 - 15:45 MDT
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14:45 MDT

What 25 Days of Optimisations Taught Me About Compilers
Friday September 18, 2026 14:45 - 15:45 MDT
In December I posted a short video every day about a different compiler optimisation. Some were obvious. Some surprised me. A handful caught me out completely, and some even were compiler bugs!

This talk distils the most interesting into one talk. It isn't a clip show: the order matters, the gaps matter, and together they tell a story about where modern optimisers are scarily good, where they're stubbornly bad, and where that gap has moved in the last few years. With outtakes about what didn't make the cut and what I got wrong on camera.

Presenters
avatar for Matt Godbolt

Matt Godbolt

Programmer and sometime verb, Compiler Explorer
Matt Godbolt is the creator of the Compiler Explorer website. He is passionate about writing efficient code. He has previously worked at a trading firm, on mobile apps at Google, run his own C++ tools company and spent more than a decade making console games. When he's not hacking... Read More →
Friday September 18, 2026 14:45 - 15:45 MDT
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14:45 MDT

Concurrency for Modern CPUs - Lock-Free or Lock-based?
Friday September 18, 2026 14:45 - 15:45 MDT
For decades, lock-free programming has been the go-to optimization for the most contended parts of concurrent programs. The reasoning was simple: locks are slow under contention, so eliminate the locks. This made sense on the hardware of the time, and I should know—I've given several talks explaining how and why to do it. The hardware has changed. Modern CPUs are highly optimized for the operations that make locks fast: cache-line transfers, memory ordering, and speculative execution through lock acquisitions. To set the stage, we will briefly establish why, under high contention, a well-written lock consistently outperforms lock-free atomics and CAS loops. (As an aside, I'll hand you a concrete recipe for a spinlock that actually holds up under extreme contention—and show why systematic backoff, by batching cache-line ownership, is what protects the shared interconnect.) But the core of this talk addresses a completely flipped reality: at low contention, lock-free code decisively outperforms spinlocks, for the most surprising reason. Conventional wisdom assumes an uncontended spinlock is practically free. Using raw hardware performance counters, we will see why it isn't: the implicit synchronization a spinlock imposes—even with no contention at all—is deeply unfavorable to modern out-of-order pipelines, while a single lock-free XADD or CAS, an indivisible read-modify-write, is not. The path everyone assumes is free turns out to be the quietly expensive one. Putting these two facts together—locks winning high contention via cache-line batching, atomics winning low contention by staying out of the pipeline's way—points to a concrete design. I will present a highly optimized MPMC (multi-producer, multi-consumer) queue built on a dual-domain structure that deliberately segregates the contended path from the uncontended one, letting each run on the mechanism the hardware actually favors. We will then walk extensive benchmarks across modern silicon—Intel, ARM server (Graviton/Grace), and Apple (M3)—showing this queue is the fastest, often by wide margins, across most operating regimes. We will also see why the tradeoffs play out so differently per chip, in ways that aren't obvious from the spec sheet, and why "ARM vs x86" is the wrong axis entirely—what matters is the chip's target market, not its instruction set. Finally, no benchmark is complete without honest caveats. I will detail the specific corners where this design can still be beaten, the hidden system costs you pay elsewhere to buy this throughput, and why systems that strictly require progress guarantees—deadlock avoidance, priority inversion, safe execution in a signal handler—mean traditional lock-free programming is not dead. It has simply relocated. If you've ever reached for a complex lock-free algorithm to speed up a highly contended hot path—or wondered what your CPU is actually doing during a mutex unlock—this talk will change your mind about where lock-free programming truly belongs.

Presenters
avatar for Fedor Pikus

Fedor Pikus

Fellow, Siemens EDA
Fedor G Pikus is a Technical Fellow and the Director of the Advanced Projects Team in Siemens Digital Industries Software. His responsibilities include planning the long-term technical direction of Calibre products, directing and training the engineers who work on these products... Read More →
Friday September 18, 2026 14:45 - 15:45 MDT
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